Abstract: Disclosed herein is a digital to analog converter including a first dynamic latch receiving a data signal and an inverse of the data signal. The first dynamic latch is clocked by a clock signal and configured to generate first and second quad switching control signals as a function of the data signal and the inverse of the data signal. A second dynamic latch receives the data signal and the inverse of the data signal, is clocked by an inverse of the clock signal, and is configured to generate third and fourth quad switching control signals as a function of the data signal and the inverse of the data signal. A quad switching bit cell is configured to generate an analog representation of the data signal as a function of the first, second, third, and fourth quad switching signals.

Abstract: A delta-sigma modulator includes a first integrator configured to integrate a sum of an input signal and a first feedback signal, a second integrator configured to integrate a sum of an output value of the first integrator and a second feedback signal, a first FIR filter circuit configured to perform a first FIR filtering on an output modulation signal and a delay modulation signal and feeds back the signals to stage prior to the first integrator, and a second FIR filter circuit configured to perform a second FIR filtering on the output modulation signal and the delay modulation signal and feeds back the signals to a stage prior to the second integrator.

Abstract: An antenna structure including a substrate, a grounding layer, a first antenna layer, a second antenna layer, an inductance element and a capacitance element is provided. The substrate has a surface. The grounding layer is formed on the surface of the substrate. The first antenna layer includes a first radiating portion and a second radiating portion. The second antenna layer includes a third radiating portion and a fourth radiating portion. The third radiating portion is connected to the first radiating portion at a connection portion. The connection portion is separated from the grounding player, and the fourth radiating portion and the second radiating portion are disposed oppositely and separated from each other. The inductance element bridges the grounding layer and the connection portion. The capacitance element bridges the fourth radiating portion and the second radiating portion.

Abstract: A method and apparatus for switching between two antenna elements in an electronic device having a hinge. A rotating element within the hinge has a coupling or contact brush that extends into contact with a first contact element connected to a first antenna element. Rotation of the hinge moves the coupling of coupled communication with the first contact element and into coupled communication with a second contact element, that connects to a second antenna element. The first and second antenna elements are provided on a hinge of an electronic device that may be moved from a closed position to a 360 degree open position or tablet position. The movement of the hinge switches between the two antenna elements to avoid blocking of the connected antenna(s) by the body of the electronic device.

Abstract: A system can include an analog input port; a digital output port; and a successive approximation register (SAR) analog-to-digital converter (ADC). The SAR ADC can include a voltage comparator Vd having a first input, a second input, and an output; a first plurality of capacitors Cp[0:n] that are coupled with the analog input port and each have a top plate and a bottom plate; a second plurality of capacitors Cn[0:n] that are coupled with the analog input port and each have a top plate and a bottom plate; and a SAR controller coupled between the output of the voltage comparator Vd and the digital output port.

Abstract: In one embodiment, an apparatus comprises a memory; and a compression engine comprising circuitry, the compression engine to assign weights to a plurality of first symbols of a data set, a weight representing a frequency of a corresponding first symbol in the data set; perform a partial sort of the first symbols based on the assigned weights; generate at least a portion of a Huffman tree based on the partial sort; and create a plurality of Huffman codes for the plurality of first symbols based on the Huffman tree.

Abstract: An inductor bridge is provided with a flexible flat plate-shaped element body, a first connector, and a second connector. The element body includes therein an inductor portion. The inductor portion is configured by a spiral conductor pattern. The first connector is provided on the element body and is connected to a first circuit. The second connector is provided on the element body and is connected to a second circuit.

Abstract: A device can include a first ground element to be electrically connected to a module including a cellular antenna. The first ground element and the module can be stackable. The cellular antenna can have a first ground plane provided by a second ground element included in the module. The first ground element can provide a second ground plane for the cellular antenna when the first ground element is electrically connected to the cellular antenna. The second ground plane can be larger than the first ground plane. Radio performance of the cellular antenna with regard to a cellular network is enhanced when the cellular antenna is electrically connected to the first ground element based on the second ground plane.

Abstract: The invention provides an analog-to-digital converter (ADC) converting an input signal to an output signal. The ADC may comprise a main circuit and a comparator coupled to the main circuit. The main circuit may: transfer the input signal by an input transfer block, filter an error signal by a loop filter, and combine the transferred input signal and the filtered error signal to form a combined signal. The comparator may quantize the combined signal to provide the output signal, wherein the error signal may reflect a difference between the combined signal and the output signal.

Abstract: Technologies for compressing data with multiple hash tables include a compute device. The compute device is to produce, for each of multiple string prefixes of different string prefix sizes, an associated hash. Each string prefix defines a set of consecutive symbols in a string that starts at a present position in an input stream of symbols. The compute device is also to write, to a different hash table for each string prefix size, a pointer to the present position in association with the associated hash. Each hash is usable as an index into the associated hash table to provide the present position of the string.

Abstract: A hybrid Analog-to-Digital Converter (ADC) has multiple stages. A first stage and a final stage each use a Successive-Approximation Register (SAR) ADC to generate the Most-Significant-Bits (MSBs) and the Least-Significant-Bits (LSBs) over successive internal cycles. Middle stage(s) use a faster flash ADC with multiple comparators in parallel to generate the middle binary bits, which are then re-converted by a Digital-to-Analog Converter (DAC) and subtracted from the stage's input analog voltage to generate a difference that is amplified by a residual amplifier that outputs an amplified voltage to the next stage. The first stage also has this multiplying DAC structure to convert the MSBs to an amplified voltage to the first of the middle stages. Finally, digital error correction logic removes redundant binary bits between stages. Initial and final SAR stages of 4 and 8 bits with a 4-bit middle stage provide a hybrid ADC of 14-bit precision.

Abstract: Embodiments disclosed include multi-band monopole planar antennas configured to facilitate radio frequency (RF) isolation in multiple-input multiple-output (MIMO) antenna arrangement. In one aspect, a multi-band monopole planar antenna is provided and configured to generate a slant 45° radiation polarization in the lower frequency band. As a result, sufficient RF isolation may be achieved in the lower frequency band when a plurality of dual-band monopole planar antennas is placed in the MIMO arrangement. In another aspect, the multi-band monopole planar antenna is configured not to support certain unused RF bands, thus facilitating height reduction in the multi-band monopole planar antenna. By configuring the dual-band monopole planar antenna to generate the slant-45 radiation polarization in the lower frequency band, a plurality of the multi-band monopole planar antennas may be placed in close proximity to each other to support MIMO operation without compromising RF performance.

Abstract: The present technology relates to an imaging element, a processing method, and an electronic device which are capable of reducing deterioration in an image quality of a captured image caused by power fluctuation. A counting unit includes a counting operation unit that performs a counting operation of counting the count value and a dummy operation unit that performs a dummy counting operation at a timing complementary to the counting operation of the counting operation unit. The present technology can be applied to, for example, an imaging element that counts a count value and performs AD conversion.

Abstract: The present disclosure discloses a method for performing an ADC phase-frequency response test including: measuring a time delay of an analog mixer and low-pass filter (MLPF) in down-converting a specific carrier frequency narrowband frequency modulation (FM) signal; determining an effective sampling frequency required by an ADC for acquiring FM signals; acquiring a high carrier frequency FM signal and a low carrier frequency FM signal before and after down-conversion is performed by the analog MLPF; and demodulating the FM signals that are acquired, correcting an initial phase of a modulation signal of the high carrier frequency FM signal and an initial phase of a modulation signal of the low carrier frequency FM signal, and calculating a phase-frequency response of the ADC at a high carrier frequency. The present disclosure has advantages of a simple test process, a wide frequency range with frequencies and a test simultaneously performed on multiple channels.

Abstract: System and methods for input path matching in pipelined continuous-time Analog-to Digital Converters (ADCs), including pipelined Continuous-Time Delta Sigma Modulator (CTDSM) based ADCs, includes an input delay circuit disposed in a continuous-time input path from an input of an analog input signal to a first summing circuit of the continuous-time ADC. At least one digital delay line is disposed between an output of an earlier stage sub-ADC (of a plurality of pipelined sub-ADCs) and a sub-digital-to-analog converter (DAC) that is coupled to the first summing circuit, and between the earlier stage sub-ADC and a digital noise cancellation filter. The digital delay line(s) is configured to enable calibration of delay of output of the earlier stage sub-ADC provided to the sub-DAC and the digital noise cancellation filter in accordance with process variations of the input delay match circuit to minimize residue output at first summing circuit.

Abstract: A method including separating multiple signal waveforms into multiple blocks forming a sequence is provided. Each of the blocks includes at least a portion of each of the multiple signal waveforms. The method includes identifying a shared time portion and a shared signal portion for the signal waveforms within a first block from the multiple blocks and selecting a format for the first block based on a block size of the first block and a block read time of the first block. The method also includes compressing data in the first block based on the shared time portion, the shared signal portion, a preceding block and a subsequent block in the sequence, and storing the first block in a memory based on the format selected for the first block.

Abstract: An interfacing circuit adaptable to an analog-to-digital converter (ADC) includes a sample and hold (S/H) circuit; an input switch; an input capacitor with a first end connected to an input end of a comparator of the ADC via the S/H circuit, and with a second end connected to receive an input signal via the input switch; a hold switch connected between the second end of the input capacitor and an original common-mode voltage; a reset switch connected between the input end of the comparator and a target common-mode voltage; and a front switch connected between the first end of the input capacitor and the target common-mode voltage.

Abstract: The resolution of a time to digital converter (TDC) is improved by using a gain stage at the input of the fine TDC. A delay line receives a pulse corresponding to the time information and recirculates the pulse in the delay line by coupling an output of the delay line to an input of the delay line. An integrating fine TDC receives a number of pulses from the delay line corresponding to the desired gain.

Abstract: A calibration method for a digital-to-analog converter (DAC) is disclosed. The DAC is applied to a successive approximation analog-to-digital converter (SA ADC) and includes a first capacitor, multiple second capacitors and a bridge capacitor. The method includes the steps of: (a) controlling voltages at two input terminals of a comparator of the SA ADC to be equal; (b) changing a voltage at a first terminal of the first capacitor; (b) obtaining a first output of the SA ADC; (d) after obtaining the first output, controlling voltages at the two input terminals of the comparator to be equal; (e) changing voltages at multiple first terminals of the second capacitors; (f) obtaining a second output of the SA ADC; and (g) calibrating the DAC according to the first output and the second output.

Abstract: A sigma delta modulator includes a sigma delta modulating loop and a plurality of adjusting loops. The sigma delta modulating loop processes an input signal and an adjustment signal based on a first clock signal, so as to generate a quantized output signal. The first clock signal has a clock cycle. The sigma delta modulating loop has a first delay time that is the same as M times of the clock cycle. M is an integral multiple of 0.5 and is larger than 1. The adjusting loops delay the quantized output signal for second delay times, respectively, so as to generate the adjustment signal.