Abstract: A system may comprise a high-pass filter having an input for receiving an input signal, an output for generating an output signal, a capacitor coupled between the input and the output, a switched-capacitor resistor coupled between the output and a reference voltage, and control circuitry configured to control the reference voltage to cancel current leakage into a circuit coupled to the output. The input, the output, the capacitor, and the switched-capacitor resistor may be arranged to generate the output signal as a high-pass filtered version of the input signal and the high-pass filter may be configured to operate in a plurality of modes comprising at least a high-impedance mode and a low-impedance mode in which the resistance of the switched-capacitor resistor is significantly smaller than the resistance when in the high-impedance mode.

Abstract: In general, embodiments of the present invention provide systems, methods and computer readable media for data record compression using graph-based techniques.

Abstract: A phased array antenna panel includes an array of antenna cells. Optionally, the phased array antenna panel includes a frame with multiple shielding fences housing the array of antenna cells. Each antenna cell includes a raised antenna patch with air dielectric. In one example, the raised antenna patch may include four projections having outwardly increasing widths, and four supporting legs, each of the four supporting legs situated between a pair of adjacent projections. A first differential feed port may be coupled to first and second supporting legs of the raised antenna patch through first and second transformers, and a second differential feed port may be coupled to third and fourth supporting legs of the raised antenna patch through third and fourth transformers. A return loss in a frequency range of between 27.5 GHz and 29.5 GHz of each antenna cell is less than about ?10 dB.

Abstract: A driver arrangement (10) comprises a digital controller (11) that is configured to receive a digital input signal (SDI) and a driver (12) that comprises a driver input (14) and a driver output (15) and is configured to provide an analog output signal (SANO) at the driver output (15). The driver arrangement (10) comprises a coupling circuit (13) that comprises a digital-to-analog converter (19) and a feedback circuit (24). The digital-to-analog converter (19) comprises a converter input (20) coupled to the digital controller (11) and a converter output (21) coupled to the driver input (14). The feedback circuit (24) is coupled to the driver output (15) and to a feedback input (17) of the digital controller (11).

Abstract: Some embodiments include apparatuses having a first circuit portion, a second circuit portion, and a third circuit portion. The first circuit portion includes a first transistor to receive a first signal of a differential signal pair and a second transistor to receive a second signal of the differential signal pair. The second circuit portion is coupled to the first and second transistors and a first supply node, the second circuit portion including a first output node and a second output node to provide an output signal pair based on the differential signal pair. The third circuit portion includes a first diode-connected transistor coupled between the first output node and a second supply node and a second diode-connected transistor coupled between the second output node and the second supply node.

Abstract: A circuit applied to speaker includes a tri-level current DAC and a class D amplifier. The current DAC is arranged to receive a digital signal to generate a current signal, and the class D amplifier is arranged to directly receive the current from the current DAC and to amplify the current signal to generate an output signal. SNR performance is well improved class D amplifier due to small signal noise reduced by preceding tri-level DAC. In addition, the circuit further includes a driving stage, and a gate-drain voltage of a power transistor within the driving stage can be controlled to set the appropriate slew rate.

Abstract: A device includes an amplifier and calibration circuitry coupled to the amplifier. The calibration circuitry is configured to receive calibration values. The calibration circuitry is also configured to generate an output value in response to receiving a timing input.

Abstract: A method and apparatus are provided for controlling an SAR ADC by generating a first signal to control sampling of an analog input voltage at a DAC, and then generating a second signal to start a successive approximation sequence at a comparator and SAR engine to convert the analog input voltage to an N-bit digital value, where the successive approximation sequence includes a settling phase for each bit of the N-bit digital value and is controlled to synchronously end in response to a first synchronous clock signal, and also includes a comparison phase for each bit of the N-bit digital value to allow for comparison of the analog input voltage to a reference voltage, where each comparison phase is controlled to synchronously start in response to the first synchronous clock signal and asynchronously end in response to a second asynchronous clock signal that is self-generated by the comparator.

Abstract: Methods and apparatus for reducing non-linearity in analog to digital converters are disclosed. An example apparatus includes an analog-to-digital converter to convert an analog signal into a digital signal; and a non-linearity corrector coupled to the analog-to-digital converter to determine a derivative of the digital signal; determine cross terms including a combination of the digital signal and the derivative of the digital signal; and determine a non-linearity term corresponding to a combination of the cross terms.

Abstract: Certain aspects of the present disclosure provide apparatus and techniques for analog-to-digital conversion using a time-to-digital converter (TDC). For example, certain aspects provide a quantizer using a TDC. The quantizer may include at least one first capacitive element and a set of switches configured to selectively couple a first terminal and a second terminal of the at least one first capacitive element to at least one input voltage source. The TDC may also include a reference voltage source, at least one switch coupled between the second terminal of the at least one first capacitive element and an output of the reference voltage source, a current source selectively coupled to the first terminal of the at least one first capacitive element, and a voltage sense circuit coupled to the first terminal of the at least one first capacitive element.

Abstract: During operation of a SAR ADC, several of the MSBs can be preloaded with predetermined bit decisions prior to carrying out bit trials. A system and method can be provided for incrementally preloading the predetermined bit decisions such as to maintain voltages present at comparator inputs within a limited range of acceptable input voltages.

Abstract: The encoding of an input string of binary characters includes: a register storing a cellular data structure definition including a starting empty cell; a register storing a group cell structure definition for a valid brick formation; a brick validation engine testing data structure at a current cell beginning with the starting empty cell for an invalid brick formation; a character reading/writing engine writing, if the empty cell is not invalid, a binary character from the input string to the empty cell and writing, if the empty cell is invalid, a dummy value to the empty cell; a loop facilitator looping back through the testing and writing steps with a next data character and a next empty cell until there are no more data characters; and a serialization de-serialization engine methodically serializing the data structure into a one dimensional binary string of characters representing an encoded string of alphanumeric characters.

Abstract: An analog-to-digital converter circuit having a simple design and capable of preventing an increase in surface area and other problems. An analog-to-digital converter circuit for converting an analog input signal to a digital quantity includes an analog-to-digital converter unit that converts analog input signals to pre-correction digital values, and a corrector unit that digitally corrects the pre-connection digital values output from the analog-to-digital converter unit. The corrector unit includes a weighting coefficient multiplier unit that outputs a post-correction digital value obtained by multiplying the weighting coefficients provided for each bit by each bit of the pre-correction digital value output from the A/D converter unit and summing them, and a weighting coefficient search unit that searches for weighting coefficients so as to minimize an error signal generated based on the post-correction digital value and an approximate value for the post-correction digital value.

Abstract: An encoder for encoding data to generate corresponding encoded data including information indicative of a frequency, probability or range of one or more symbols to be represented in the encoded data. The encoder can include in the encoded data additional information indicative of whether information indicative of a frequency, probability or range for at least one symbol amongst the one or more symbols is in the encoded data. The encoder can include in the encoded data the additional information of whether information indicative of a frequency, probability or range for at least one symbol amongst the one or more symbols in the encoded data expressed as single availability bit information. The encoder can represent inclusion of information indicative of the frequency, probability or range information by use of a single availability bit value “7”, and non-inclusion of information indicative of the frequency, probability or range information by use of a single availability bit value “0”.

Abstract: An apparatus may include a circuit configured to generate, by an analog to digital converter (ADC), one or more ADC samples based on an input signal. The circuit may be further configured to generate a first estimated signal using a first channel pulse response estimation with a gain constraint based on the one or more ADC samples and generate a second estimated signal using a second channel pulse response estimation with a phase constraint based on the one or more ADC samples.

Abstract: A semiconductor device having an analog/digital conversion circuit converting an analog signal to a digital signal, includes a holding circuit outputting an analog signal having a value according to a value of an analog signal supplied in a first period; and a prediction circuit generating a first digital signal based on bit position information from a prediction table corresponding to the supplied analog signal.

Abstract: Techniques and apparatus for performing an invariant-reference compression/decompression process are described. In one embodiment, for example an apparatus to generate invariant-reference compressed data may include at least one memory and logic, at least a portion of comprised in hardware coupled to the at least one memory, the logic to access input data comprising a plurality of literals and a plurality of repeating sequences, and perform an invariant-reference compression process to generate the invariant-reference compressed data, the invariant-reference compression process comprising determining a relative distance for each of the plurality of repeating sequences, the relative distance comprising a bit offset in the invariant-reference compressed data, and encoding each of the plurality of repeating sequences as a reference token in the invariant-reference compressed data, the reference token comprising the relative distance and a length. Other embodiments are described and claimed.

Abstract: A system for data decompression may include a processor coupled to a remote memory having a remote dictionary stored thereon and coupled to a decompression logic having a local memory with a local dictionary. The processor may decompress data during execution by accessing the local dictionary, and if necessary, the remote dictionary.

Abstract: The invention introduces a method for accelerating compression, performed in a compression accelerator, including: repeatedly executing a loop for determining the longest matched-length between a first string and a second string. Each iteration of the loop includes: obtaining n successive characters from the first string as a source string, wherein n is greater than 1; comparing each character of the source string with all characters of the second string, so as to generate n first-match-results corresponding to the n successive characters of the source string respectively; generating a second-match-result according to the n first-match-results; and determining whether a continuous match of the n successive characters is presented according to the second-match-result. If so, n is added to the matched length and the next iteration of the loop is continued to execute. Otherwise, a matched length is updated and output and the loop is exited.

Abstract: Disclosed are systems and methods for identifying and reporting failures of an analog-to-digital converter (ADC). Specifically, the systems and methods described herein evaluate quantization noise properties of ADCs, including delta-sigma ADCs and successive approximation register (SAR) ADCs, to verify functionality and/or identify failures. Quantization noise properties can be evaluated in the frequency domain by, for example, comparing RMS values, magnitudes, frequency spectrums, and the like, in various frequency bands to threshold values and/or to verify an expected noise shape. Quantization noise properties can additionally or alternatively be evaluated in the time domain by, for example, comparing counts of pulse widths, average pulse widths, and/or number of transitions within a sequence of pulses to threshold values and/or to similar identifiable characteristics in other pulse width bands.