Abstract: The embodiments herein provide a multiband reconfigurable filtenna comprising a monopole antenna coupled to a center split transmission line and a reconfigurable microstrip filter replacing a feed-in end of the center split transmission line to provide resonance to the monopole antenna at a plurality of frequency bands. The reconfigurable microstrip filter includes a C-shaped resonator (CSR), a meandered loop resonator (MLR), an Inverted Pulse Shaped Resonator (IPSR) and an Open Circuited Stub (OCS). Further, a plurality of switches is coupled to the reconfigurable microstrip filter to switch coupling of the monopole antenna between the CSR, the MLR, the IPSR and the OCS for operating the monopole antenna, at one of the plurality of frequency bands.

Abstract: An electronic device may include a ring-shaped housing member defining an interior volume. The ring-shaped housing member may be configured to receive electronic device components. The ring-shaped housing member may include a first element comprising an angled region, and a second element comprising an angled region. A first intermediate element may be placed between the first and second elements, where the intermediate element is secured to internal surfaces of each of the first and second elements such that the first and second elements do not overlap. The first intermediate element may fasten the first and second elements to one another, and electrically isolate the first and second elements from one another.

Abstract: Systems, methods, and computer-readable media are described for performing data compression in a manner that does not require software to make a call to hardware to close a compressed data block, thereby reducing computational overhead. In response to a request from software to data compression hardware for a data encoding, the hardware may return the data encoding as well as an end-of-block symbol encoding value and bit length. The hardware may load the end-of-block symbol encoding value and bit length into a different area in the returned structure such that the software has direct access to the value. When the software determines that a block should be closed, the software may retrieve the end-of-block symbol and insert it into the block without needing to make a call to hardware. The software may then make a call to the hardware to request a new data encoding for subsequent compressed data blocks.

Abstract: Implementations of antennas may include a meandering T-matching structure, a first meandering feed line coupled to the meandering T-matching structure, and a first radiating part coupled to the first meandering feed line. Implementations may include a second meandering feed line coupled to the meandering T-matching structure, and a second radiating part coupled to the meandering feed line. A gap may physically separate the first meandering feed line and the second meandering feed line.

Abstract: In an architecture for processing data comprising a control unit and converters CNj to be synchronized to an active front of a common reference clock CLK, the synchronizing method makes provision for the converters to be arranged in at least one series chain, and for a procedure for synchronizing the converters by propagating a synchronizing signal SYNC-m emitted by the control unit, said signal being retransmitted as output OUT by each converter, after resynchronization to a clock active front, to a synchronization input IN of a following converter in the chain. Each converter comprises a synchronization configuration register REG containing at least one polarity parameter Sel-edgej that sets the polarity of the reference-clock front for reliable detection of a synchronizing signal received via the input of the converter.

Abstract: In general, embodiments of the present invention provide systems, methods and computer readable media for data record compression using graph-based techniques.

Abstract: Electronic devices may be provided with antenna arrays and wireless circuitry for handling wireless communications in satellite communications bands and other frequency bands of interest. A portable electronic device may have a housing with a peripheral edge. An array of antennas in the portable device may extend along the peripheral edge and may be coupled (directly or indirectly) to wireless circuitry that transmits and receives satellite communications signals and/or other wireless communications signals. The antennas may include dipole antennas. The dipole antennas may include edge dipole antennas with straight arms that extend parallel to one or more peripheral housing edges. Additionally or alternatively, the dipole antennas may include corner dipole antennas at the corners of the housing. The corner dipole antennas may have arms with bent tips. A ground plane in the center of the electronic device may serve as a reflector for the peripheral dipole antennas.

Abstract: A wearable wireless communication device comprises a transceiver positioned on a first side of the device, the transceiver comprising a first antenna configured to receive radio frequency (RF) signals transmitted toward the first side of the device. The device is wearable about an object that attenuates reception, by the first antenna, of RF signals transmitted toward a second side of the device. The device further comprises a waveguide electromagnetically coupled to the transceiver, the waveguide terminating in at least a second antenna positioned on the second side of the device. The second antenna is configured to receive the RF signals transmitted toward the second side of the device. The waveguide is shaped to direct received RF signals around the object to the transceiver. The object may in some embodiments be a piece of human anatomy.

Abstract: An antenna device includes: a plurality of cores arranged in series; a coil; and a capacitor connected to the coil, in which a first core, which is selected from the plurality of cores, and a second core, which is selected from the plurality of cores and is arranged on any one end portion side of the first core, are arranged apart from each other, and in which at least one end surface, which is selected from an end surface of the first core on a side on which the second core is arranged and an end surface of the second core on a side on which the first core is arranged, is located on an inner peripheral side of the coil.

Abstract: Systems and methods are provided for digital-to-analog conversions with adaptive digital offsets. A digital offset may be determined and applied to a digital input to a digital-to-analog converter (DAC), and digital-to-analog conversions are then applied via the DAC to the digital input with the digital offset. The digital offset may be set to account for one or more conditions relating to inputs to the DAC, with the one or more conditions affecting switching characteristics of one or more of a plurality of conversion elements in the DAC. The digital offset may be determined dynamically and adaptively, such as based on the input and/or conditions relating to the input. The adjustments may be selectively applied to the digital offset for particular input conditions.

Abstract: A time-interleaved digital-to-analog converter (DAC) uses M DAC cores to convert a digital input signal whose digital input words are spread to different DAC cores to produce a final analog outputs. The M DAC cores, operating in a time-interleaved fashion, can increase the sampling rate several times compared to the sampling rate of just one DAC. However, sequential time-interleaving DAC cores often exhibit undesirable spurs at the output. To spread those spurs to the noise floor, the time-interleaving DAC cores can be selected at a pseudo randomized manner or in a specific manner which can break up the sequential or periodic manner of selecting the DAC cores.

Abstract: A comparator includes a differential input pair of transistors, a pair of cross coupled n-channel metal-oxide-semiconductor field-effect (NMOS) transistors, a pair of p-channel metal-oxide semiconductor field-effect (PMOS) transistors, a first inverter, and a second inverter. The differential input pair of transistors includes a first input transistor and a second input transistor. The pair of cross coupled NMOS transistors includes a first NMOS transistor and a second NMOS transistor. The pair of PMOS transistors includes a first PMOS transistor and a second PMOS transistor. The pair of PMOS transistors are coupled to the pair of cross coupled NMOS transistors. The first inverter is coupled in series with the first PMOS transistor. The second inverter is coupled in series with the second PMOS transistor.

Abstract: A system and method is provided for image sensing. The image sensing system includes a comparator for comparing an input signal representing a sensed light signal from at least one pixel of the image sensing system and a reference signal. The comparator includes at least one digital transistor.

Abstract: A multibit flash quantizer circuit, such as included as a portion of delta-sigma conversion circuit, can be operated in a dynamic or configurable manner. Information indicative of at least one of an ADC input slew rate or a prior quantizer output code can be used to establish a flash quantizer conversion window. Within the selected conversion window, comparators in the quantizer circuit can be made active. Comparators outside the conversion window can be made dormant, such as depowered or biased to save power. An output from such dormant converters can be preloaded and latched. In this manner, full resolution is available without requiring that all comparator circuits within the quantizer remain active at all times.

Abstract: Methods and systems for generating a digital representation of the amplitude and phase of a bandpass signal are disclosed. The methods comprise filtering the bandpass signal with a bandpass filter, generating the real and imaginary parts of the complex analytic signal with a quadrature hybrid, determining the amplitude of the complex analytic signal by adding an even power-law transform of the real and imaginary parts of the complex analytic signal, and determining the phase of the complex analytic signal by comparing the real and imaginary parts of the complex analytic signal to zero and comparing an even power-law transform of the real and imaginary parts of the complex analytic signal to each other. Analog to digital converters and methods of converting complex analytic signals to digital signals are also disclosed.

Abstract: The present invention provides a program counter compression method and a hardware circuit thereof. The compression method of the present invention includes the following steps: step (1), acquiring execution condition of instructions sent by a processor and classifying and screening said instructions based on said execution condition of the instructions; step (2), executing differential operation on instruction count values of the objective classification and the stall periods based on the classifying and screening result and splicing the obtained differential values; step (3), dictionary encoding the valid differential slicing data segments recorded in step (2). The present invention effectively combines the architecture compression and non-architecture compression and proposes a three-stage compression scheme by organizing and applying classifying and screening, differential encoding and dictionary compression, which drastically increases the compression ratio of the program counter.

Abstract: According to the embodiments described herein, a stretchable RFID device can include an RFID chip and an RFID antenna. The RFID antenna can be electrically coupled and mechanically attached to the RFID chip. The RFID antenna can be impedance matched to the RFID chip across a broad bandwidth and can include two arms. Each of the two arms can include an end-loading body that at least partially surrounds an end-loading orifice. The end-loading body can stretch without consuming the end-loading orifice.

Abstract: Technologies for performing speculative decompression include a managed node to decode a variable size code at a present position in compressed data with a deterministic decoder and concurrently perform speculative decodes over a range of subsequent positions in the compressed data, determine the position of the next code, determine whether the position of the next code is within the range, and output, in response to a determination that the position of the next code is within the range, a symbol associated with the deterministically decoded code and another symbol associated with a speculatively decoded code at the position of the next code.

Abstract: The present disclosure provides a device for wireless access, which pertains to the technical field of wireless network. The device for wireless access includes a device body; a radio frequency circuit disposed inside the device body; and a plurality of antenna units disposed on an external surface of the device body, each of the plurality of antenna units being connected to the radio frequency circuit; wherein each of the plurality of antenna units comprises an antenna oscillator, and the antenna oscillators on each two adjacent antenna units of the plurality of antenna units are misaligned with each other. By disposing antenna oscillators of adjacent antenna units on the misaligned regions of the respective antenna unit, the interference of co-frequency signals between adjacent antenna units may be reduced, and the isolation of adjacent antenna units may be enhanced. Thus, adjacent antenna units may be disposed at a reduced distance therebetween.

Abstract: In one embodiment, a multi-beam antenna is described. The multi-beam antenna includes a reflector having a single reflector surface defining a first focal region and a second focal region. A first feed group is located within the first focal region. The first feed group includes a first feed oriented relative to the reflector define a first beam pointed in a first direction. The multi-beam antenna further includes a fixed attachment mechanism attaching the first feed group to the reflector such that a position of the first feed group is fixed relative to the reflector. The multi-beam antenna further includes a second feed group located within the second focal region. The second feed group includes a second feed oriented relative to the reflector to define a second beam pointed in a second direction.