Patents Examined by Hung Vu
  • Patent number: 10276534
    Abstract: A first electrical contact and second contact is upon an interposer and/or upon a processing device. The first contact includes a minor axis and a major axis. The second contact includes diameter axes. The first contact is positioned such that the major axis is generally aligned with the direction of expansion of the interposer and/or the processing device. The first electrical contact may further be positioned within a power/ground or input/output (I/O) region of the interposer and/or processing device. The first electrical contact may further be positioned within a center region that is surrounded by a perimeter region of the interposer and/or the processing device. The dimensions or aspect ratios of major and minor axes of neighboring first electrical contacts within an electrical contact grid may differ relative thereto. Further, the angle of respective major and minor axes of neighboring first electrical contacts within the electrical contact grid may differ relative thereto.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: April 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Anson J. Call, Vijayeshwar D. Khanna, David J. Russell, Krishna R. Tunga
  • Patent number: 10276535
    Abstract: An electrical contact upon an interposer and/or upon a processing device includes a minor axis and a major axis. The contact is positioned such that the major axis is generally aligned with the direction of expansion of the interposer and/or the processing device. The electrical contact may further be positioned within a power/ground or input/output (I/O) region of the interposer and/or processing device. The electrical contact may further be positioned within a center region that is surrounded by a perimeter region of the interposer and/or the processing device. The dimensions or aspect ratios of major and minor axes of neighboring electrical contacts within an electrical contact grid may differ relative thereto. Further, the angle of respective major and minor axes of neighboring electrical contacts within the electrical contact grid may differ relative thereto.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: April 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Anson J. Call, Vijayeshwar D. Khanna, David J. Russell, Krishna R. Tunga
  • Patent number: 10269729
    Abstract: A device (e.g., a Doherty amplifier) housed in an air cavity package includes one or more isolation structures over a surface of a substrate and defining an active circuit area. The device also includes first and second adjacent circuits within the active circuit area, first and second leads coupled to the isolation structure(s) between opposite sides of the package and electrically coupled to the first circuit, third and fourth leads coupled to the isolation structure(s) between the opposite sides of the package and electrically coupled to the second circuit, a first terminal over the first side of the package between the first lead and the third lead, a second terminal over the second side of the package between the second lead and the fourth lead, and an electronic component coupled to the package and electrically coupled to the first terminal, the second terminal, or both the first and second terminals.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: April 23, 2019
    Assignee: NXP USA, Inc.
    Inventors: Shun Meen Kuo, Paul R. Hart, Margaret A. Szymanowski
  • Patent number: 10263177
    Abstract: The vertical Hall element includes: a second conductivity type semiconductor layer formed on a first conductivity type semiconductor substrate; a plurality of high-concentration second conductivity type electrodes formed in a straight line on a surface of the semiconductor layer having substantially the same shape, and spaced at a first interval; a plurality of electrode isolation layers each formed between two electrodes out of the plurality of electrodes to isolate the plurality of electrodes from one another having substantially the same shape, and spaced at a second interval; and a first added layer and a second added layer each formed along the straight line outside of the outermost electrodes, and each having substantially the same structure as that of each electrode isolation layer.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: April 16, 2019
    Assignee: ABLIC INC.
    Inventors: Takaaki Hioka, Mika Ebihara
  • Patent number: 10263047
    Abstract: A display device includes plural unit areas each of which includes low definition pixels as sub-pixels larger than a specified standard and high definition pixels as sub-pixels smaller than the specified standard and which are regularly arranged. The low definition pixels include a blue pixel and a red pixel, and the high definition pixels include a white pixel and a green pixel.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: April 16, 2019
    Assignee: Japan Display Inc.
    Inventor: Toshihiro Sato
  • Patent number: 10249837
    Abstract: Provided is a light-emitting element having a light-emitting layer which contains at least a host material and a plurality of guest materials, where the host material has a lower T1 level than that of at least one of the plurality of guest materials. The emission of the one of the plurality of guest materials exhibits a multicomponent decay curve, and the lifetime thereof is less than or equal to 15 ?sec, preferably less than or equal to 10 ?sec, more preferably less than or equal to 5 ?sec, where the lifetime is defined as a time for the emission to decrease in intensity to 1/100 of its initial intensity.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: April 2, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takeyoshi Watabe, Satoshi Seo
  • Patent number: 10237977
    Abstract: A method includes forming a multi-stacked electronic device having two or more electronic components, each of the electronic components includes a leadframe, the leadframes of each electronic component are physically joined together using a non-solder metal joining process to form a joint, and the joint is located outside a solder connection region.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: March 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Ai Kiar Ang, Michael Lauri
  • Patent number: 10229957
    Abstract: The present invention relates inter alia to a color display comprising nanoparticles and color filters.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: March 12, 2019
    Assignees: MERCK PATENT GMBH, YISSUM RESEARCH DEVELOPMENT COMPANY OF THE HEBREW UNIVERSITY OF JERUSALEM, LTD.
    Inventors: Bernhard Rieger, Edgar Boehm, Volker Hilarius, Christof Pflumm, Uri Banin
  • Patent number: 10231334
    Abstract: A method includes forming a multi-stacked electronic device having two or more electronic components, each of the electronic components includes a leadframe, the leadframes of each electronic component are physically joined together using a non-solder metal joining process to form a joint, and the joint is located outside a solder connection region.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: March 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Ai Kiar Ang, Michael Lauri
  • Patent number: 10224361
    Abstract: A light receiving region includes a plurality of light detecting sections 10. The light detecting sections 10 has a second contact electrode 4A. The second contact electrode 4A is arranged at a position overlapping a first contact electrode 3A, so as to contact the first contact electrode. Further, a resistive layer 4B is continued to the second contact electrode 4A.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: March 5, 2019
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Koei Yamamoto, Terumasa Nagano, Kazuhisa Yamamura, Kenichi Sato, Ryutaro Tsuchiya
  • Patent number: 10224269
    Abstract: A module includes a laminate, the laminate including a solder mask layer and at least one depression in an upper surface of the solder mask layer that does not pass all of the way through the solder mask layer. The module also includes a first electronic element disposed in a first of the at least one depressions.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: March 5, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles L. Arvin, Brian M. Erwin, Brian W. Quinlan
  • Patent number: 10224283
    Abstract: A semiconductor device includes a metal-containing structure such as a copper-containing wire or plug and a composite capping layer formed over the metal-containing structure. The composite capping layer includes a manganese-containing layer disposed over the metal-containing structure, a silicon-containing low-k dielectric layer disposed over the manganese-containing layer, and an intermediate layer between the manganese-containing layer and the silicon-containing low-k dielectric layer. The intermediate layer is the reaction product of the manganese-containing layer and the silicon-containing low-k dielectric layer.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: March 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Donald F. Canaperi, Son V. Nguyen, Takeshi Nogami, Deepika Priyadarshini
  • Patent number: 10224500
    Abstract: An organic electronic device includes an organic device including an organic material, a first protective film on the organic device, a second protective film on the first protective film and including a same material as the first protective film, and a third protective film on the second protective film.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: March 5, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ryuichi Satoh, Kyusik Kim, Kyung Bae Park, Yong Wan Jin, Chuljoon Heo
  • Patent number: 10218316
    Abstract: A flip chip circuit comprising: a semiconductor substrate; a power amplifier provided on the semiconductor substrate; and a metal pad configured to receive an electrically conductive bump for connecting the flip chip to external circuitry. At least a portion of the power amplifier is positioned directly between the metal pad and the semiconductor substrate.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: February 26, 2019
    Assignee: NXP B.V.
    Inventors: Gian Hoogzaad, Tony Vanhoucke, Mark Pieter van der Heijden
  • Patent number: 10217874
    Abstract: Method of encapsulating a semiconductor structure comprising providing a semiconductor structure comprising an opto-electric element located in a cavity formed between a substrate and a cap layer, the cap layer being made of a material transparent to light, and having a flat upper surface; forming at least one protrusion on the cap layer; bringing the at least one protrusion of the cap layer in contact with a tool having a flat surface region, and applying a opaque material to the semiconductor structure where it is not in contact with the tool; and removing the tool thereby providing an encapsulated optical semiconductor device having a transparent window integrally formed with the cap layer.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: February 26, 2019
    Assignee: MELEXIS TECHNOLOGIES NV
    Inventors: Carl Van Buggenhout, Jian Chen
  • Patent number: 10211143
    Abstract: Highly reliable interconnections for microelectronic packaging. In one embodiment, dielectric layers in a build-up interconnect have a gradation in glass transition temperature; and the later applied dielectric layers are laminated at temperatures lower than the glass transition temperatures of the earlier applied dielectric layers. In one embodiment, the glass transition temperatures of earlier applied dielectric films in a build-up interconnect are increased through a thermosetting process to exceed the temperature for laminating the later applied dielectric films. In one embodiment, a polyimide material is formed with embedded catalysts to promote cross-linking after a film of the polyimide material is laminated (e.g., through photo-chemical or thermal degradation of the encapsulant of the catalysts).
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: February 19, 2019
    Assignee: Intel Corporation
    Inventor: Ravindra V. Tanikella
  • Patent number: 10211373
    Abstract: A light-emitting device comprises a light-emitting stack comprising a first surface, a roughened surface, and a sidewall connecting the first surface and the roughened surface; an electrode structure formed on the roughened surface of the light-emitting stack; a dielectric layer formed on the first surface of the light-emitting stack; a barrier layer covering the dielectric layer; a first reflective electrode between the barrier layer and the first surface of the light-emitting stack; and a passivation layer covering the sidewall of the light-emitting stack and the roughened surface of the light-emitting stack which is not occupied by the electrode structure, wherein the electrode structure is surrounded by the passivation layer, and the passivation layer contacts an surface of the electrode structure and terminates at the surface of the electrode structure.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: February 19, 2019
    Assignee: EPISTAR CORPORATION
    Inventors: Jan Way Chien, Tzchiang Yu, Hsiao Yu Lin, Chyi Yang Sheu
  • Patent number: 10211138
    Abstract: A multi-level semiconductor device and a method of fabricating a multi-level semiconductor device involve a first interlayer dielectric (ILD) layer with one or more metal lines formed therein. A silicide is formed on a surface of the first ILD layer and is directly adjacent to each of the one or more metal lines on both sides of each of the one or more metal lines. A second ILD is formed above the silicide, and a via is formed through the second ILD above one of the one or more metal lines. One or more second metal lines are formed above the second ILD, one of which is formed in the via. The second metal line in the via contacts the one of the one or more metal lines and the silicide adjacent to the one of the one or more metal lines.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: February 19, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin D. Briggs, Jessica Dechene, Elbert Huang, Joe Lee
  • Patent number: 10211320
    Abstract: A method of forming semiconductor fins is provided. Sacrificial fins are provided on a surface of substrate. A hard mask layer, formed around the sacrificial fins and the gaps therebetween, is made coplanar with a topmost surface of the sacrificial fins. A fin cut mask then covers a portion of the sacrificial fins and partly covers a sacrificial fin. Trenches are formed in the hard mask layer by removing sacrificial fins not covered by the fin cut mask and that portion of the sacrificial fin not partly covered by the fin cut mask. Spacers are formed on the sidewalls of the trenches and a plug is formed in the trench formed by removing that portion of the sacrificial fin not partly covered by the fin cut mask. Semiconductor fins are grown epitaxially in the trenches having the spacers from the exposed surface of the substrate upward.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: February 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Pouya Hashemi, Alexander Reznicek, Dominic J. Schepis
  • Patent number: 10204918
    Abstract: A memory device includes a memory cell on a first region of a substrate. An active region is in a second region neighboring the first region of the substrate, and an extension direction of the active region has an acute angle with the <110> direction of the substrate. A transistor serving as a peripheral circuit is on the second region of the substrate. In the memory device, defects or failures due to a crystal defects or a dislocation of the substrate may decrease.
    Type: Grant
    Filed: October 5, 2016
    Date of Patent: February 12, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Hun Lee, Jong-Ho Park, Joon-Hee Lee, Hee-Jueng Lee