Abstract: There is provided a solid-state imaging apparatus including a plurality of photoelectric conversion regions which photoelectrically convert light incident from a rear surface side of a semiconductor substrate, element isolation regions formed between the plurality of photoelectric conversion regions arranged in a matrix shape, and shielding members formed on upper surfaces of the element isolation regions. The element isolation regions have high impurity concentration regions of a high impurity concentration connected to at least a part of the shielding members.

Abstract: A semiconductor manufacturing apparatus, which is provided with a first storage chamber that stores a substrate to be processed, a second storage chamber that stores a dummy substrate, a substrate support apparatus with a heating function that supports a substrate, and a substrate transport apparatus that transports the substrates between the storage chambers and the substrate support apparatus, is further provided with a controller which, in the event that the temperature of substrate processing in a preceding substrate processing step is higher than the temperature of substrate processing in a subsequent substrate processing step, operates the substrate transport apparatus to transport the dummy substrate, whose temperature is lower than the temperature of substrate processing in the preceding substrate processing step, prior to carrying out the subsequent substrate processing step.

Abstract: An array substrate includes: a base substrate; a sub-pixel region on the base substrate in which a first electrode and a second electrode are disposed; and a first insulating layer between the first electrode and the second electrode for insulating the first electrode and the second electrode. One of the first electrode and the second electrode is a common electrode and the other is a pixel electrode. A surface of at least one of the first electrode and the second electrode is a curved surface. The array substrate is intended to provide a liquid crystal panel and a display device with high light transmittance in sub-pixel regions. A manufacturing method of an array substrate is further disclosed.

Abstract: A method for manufacturing a flexible organic light emitting display is disclosed. The method is: sequentially forming a first buffer layer, a switch array layer, a display unit layer, and a thin film package layer on a flexible underlay substrate. When the flexible organic light emitting display bends along the flexible underlay substrate, a first bending deformation force is generated. The first buffer layer is used to absorb the first bending deformation force, and the material of the first buffer layer is an organic insulating material.

Abstract: A structure comprises a first semiconductor chip with a first metal bump and a second semiconductor chip with a second metal bump. The structure further comprises a solder joint structure electrically connecting the first semiconductor chip and the second semiconductor chip, wherein the solder joint structure comprises an intermetallic compound region between the first metal bump and the second metal bump, wherein the intermetallic compound region is with a first height dimension and a surrounding portion formed along exterior walls of the first metal bump and the second metal bump, wherein the surrounding portion is with a second height dimension, and wherein the second height dimension is greater than the first height dimension.

Abstract: An integrated circuit package includes an electromagnetic communication link formed by a portion of a lead frame within an encapsulation. The lead frame includes a first conductor forming a first conductive loop a second conductor forming a second conductive loop galvanically isolated from the first conductive loop. The second conductive loop is magnetically coupled to the first conductive loop to provide a magnetic communication link between the first and second conductors. A first transceiver circuit includes a transmit circuit coupled to the first conductive loop. A second transceiver circuit includes a receive circuit coupled to the second conductive loop. A signal transmitted from the transmit circuit included in first transceiver circuit and coupled to the first conductor is coupled to be magnetically communicated through the magnetic communication link to the receive circuit included in second transceiver circuit and coupled to the second conductor.

Abstract: A chip package includes a patterned conducting plate having a plurality of conducting sections electrically separated from each other, a plurality of conducting pads disposed on an upper surface of the patterned conducting plate, wherein a recess extending from a surface of one of the conducting pads towards an inner portion of the corresponding one of the conducting pads, a chip disposed on the conducting pads, a plurality of conducting bumps disposed on a lower surface of the patterned conducting plate, wherein each of the conducting bumps is electrically connected to a corresponding one of the conducting sections of the patterned conducting plate, and an insulating support layer partially surrounding the conducting bumps.

Abstract: According to one embodiment, a semiconductor device includes a stacked body of N (N is an integer of 2 or more) layers stacked on a semiconductor substrate and openings different in depth surrounded by the stacked body and separated from each other.

Abstract: A low noise infrared photodetector has an epitaxial heterostructure that includes a photodiode and a transistor. The photodiode includes a high sensitivity narrow bandgap photodetector layer of first conductivity type, and a collection well of second conductivity type in contact with the photodetector layer. The transistor includes the collection well, a transfer well of second conductivity type that is spaced from the collection well and the photodetector layer, and a region of first conductivity type between the collection and transfer wells. The collection well and the transfer well are of different depths, and are formed by a single diffusion.

Abstract: A semiconductor process for forming a plug includes the following steps. A dielectric layer having a recess is formed on a substrate. A titanium layer is formed to conformally cover the recess. A first titanium nitride layer is formed to conformally cover the titanium layer, thereby the first titanium nitride layer having first sidewall parts. The first sidewall parts of the first titanium nitride layer are pulled back, thereby second sidewall parts being formed. A second titanium nitride layer is formed to cover the recess. Moreover, a semiconductor structure formed by said semiconductor process is also provided.

Abstract: Embodiments relate to an organic light emitting display device according to the present disclosure including: a plurality of pixels which includes red, white, blue, and green sub-pixels; driving transistor, each of which is disposed in each sub-pixel; and organic light emitting diodes, each of which is disposed corresponding to each sub-pixel, wherein a first step portion, first and second bank layers, and a first step compensation portion are disposed between the white sub-pixel and a sub-pixel adjacent thereto, thereby having an effect of suppressing a short circuit defect and a light leakage defect. In addition, an organic light emitting display device according to the present disclosure includes: red, white, blue, and green sub-pixels; at least one step portion between the sub-pixels; first and second bank layers; and a step compensation portion, thereby having an effect of suppressing a short circuit defect and a light leakage defect.

Abstract: Some embodiments of the present disclosure disclose a method for forming semiconductor packages. The method includes disposing a plurality of semiconductor chips over a top side of a wafer, molding the plurality of semiconductor chips with a first molding material, and after molding the semiconductor chips, forming a composite layer over the plurality of semiconductor chips.

Abstract: A multi-level semiconductor device and a method of fabricating a multi-level semiconductor device involve a first interlayer dielectric (ILD) layer with one or more metal lines formed therein. A silicide is formed on a surface of the first ILD layer and is directly adjacent to each of the one or more metal lines on both sides of each of the one or more metal lines. A second ILD is formed above the silicide, and a via is formed through the second ILD above one of the one or more metal lines. One or more second metal lines are formed above the second ILD, one of which is formed in the via. The second metal line in the via contacts the one of the one or more metal lines and the silicide adjacent to the one of the one or more metal lines.

Abstract: A non-volatile memory device includes a charge trapping layer for trapping charges. The charge trapping layer includes a linker layer formed over a substrate and including linkers to be bonded to metal ions metallic nanoparticles formed out of the metal ions over the linker layer and a nitride filling gaps between the metallic nanoparticles.

Abstract: A non-volatile memory device includes a floating gate for charging and discharging of charges over a substrate. The floating gate comprises a linker layer formed over the substrate and including linkers to be bonded to metal ions and metallic nanoparticles formed out of the metal ions over the linker layer.

Abstract: Provided is a light-emitting device which can emit monochromatic light with high purity due to a microcavity effect and which can emit white light in the case of a combination of monochromatic light. Provided is a high-definition light-emitting device. Provided is a light-emitting device with low power consumption. In a light-emitting device with a white-color filter top emission structure, one pixel is formed of four sub-pixels of RBGY, an EL layer includes a first light-emitting substance which emits blue light and a second light-emitting substance which emits light corresponding to a complementary color of blue, and a semi-transmissive and semi-reflective electrode (an upper electrode) is formed so as to cover an edge portion of the EL layer.

Abstract: A first metal layer of a semiconductor device includes a plurality of first metal lines that each extend along a first axis, and a first rail structure that extends along the first axis. The first rail structure is physically separated from the first metal lines. A second metal layer is located over the first metal layer. The second metal layer includes a plurality of second metal lines that each extend along a second axis orthogonal to the first axis, and a second rail structure that extends along the first axis. The second rail structure is physically separated from the second metal lines. The second rail structure is located directly over the first rail structure. A plurality of vias is located between the first metal layer and the second metal layer. A subset of the vias electrically interconnects the first rail structure to the second rail structure.

Abstract: An electronic device is provided. The electronic device includes a semiconductor layer, a dielectric layer disposed on the semiconductor layer, circuitry disposed on the dielectric layer that includes interconnected cells, first contact line metallization and second contact line metallization, first power metallization disposed in-plane with or above the circuitry and second power metallization disposed in a trench defined in at least the dielectric layer. The electronic device further includes insulation disposed to insulate the second power metallization from the circuitry and the first power metallization at first locations and to permit electrical communication between the second power metallization, the circuitry and the first power metallization at second locations.

Abstract: An improved leadframe assembly for use in a quad flat no lead (QFN) package is described along with a method of fabricating both the leadframe assembly and the QFN package. The leadframe assembly comprises an etch-stop layer formed on a topside of a substrate and a routing layer (or trace) formed on a topside of the etch-stop layer. The etch-stop layer prevents etching of an underside of the routing trace and the leadframe assembly may also comprise a top plating layer formed on a topside of the routing layer and which prevents etching of the topside of the routing trace.

Abstract: An array substrate and a display apparatus including the array substrate. The array substrate includes: a plurality of signal lines aligned in a display area of the array substrate; a plurality of signal pads aligned in a non-display area of the array substrate; a plurality of fan-out lines aligned in the non-display area and respectively connected to the signal lines and the signal pads; a plurality of auxiliary lines respectively overlapping and insulated from the fan-out lines; and a plurality of connection lines connecting in parallel at least two of the auxiliary lines that are adjacent to each other.