Patents Examined by Ishwarbhai B. Patel
  • Patent number: 12010794
    Abstract: A printed wiring board includes a base insulating layer, a conductor layer formed on the base insulating layer and including conductor pads, a solder resist layer formed on the base insulating layer such that the solder resist layer is covering the conductor layer and having openings exposing the conductor pads, respectively, and plating bumps formed on the conductor pads such that each of the plating bumps includes a base plating layer formed in a respective one of the openings of the solder resist layer, and a top plating layer formed on the base plating layer. The plating bumps are formed such that the base plating layer has an upper surface and a side surface including a portion protruding from the solder resist layer and having a rough surface and that the top plating layer has a hemispherical shape and is covering only the upper surface of the base plating layer.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: June 11, 2024
    Assignee: IBIDEN CO., LTD.
    Inventor: Satoru Kawai
  • Patent number: 11999001
    Abstract: A microelectronic assembly includes a first substrate having a surface and a first conductive element and a second substrate having a surface and a second conductive element. The assembly further includes an electrically conductive alloy mass joined to the first and second conductive elements. First and second materials of the alloy mass each have a melting point lower than a melting point of the alloy. A concentration of the first material varies in concentration from a relatively higher amount at a location disposed toward the first conductive element to a relatively lower amount toward the second conductive element, and a concentration of the second material varies in concentration from a relatively higher amount at a location disposed toward the second conductive element to a relatively lower amount toward the first conductive element.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: June 4, 2024
    Assignee: Adeia Semiconductor Technologies LLC
    Inventor: Cyprian Emeka Uzoh
  • Patent number: 12004292
    Abstract: A printed circuit board includes: a first multilayer substrate including first and second vias adjacent to each other in a stacking direction of the printed circuit board; a second multilayer substrate disposed on the first multilayer substrate in the stacking direction and including third and fourth vias adjacent to each other in the stacking direction; and an adhesive layer connecting respective one surfaces of the first and second multilayer substrates to each other. Each of the first to fourth vias has one surface and the other surface facing the one surface, the one surface being closer to the adhesive layer than the other surface, and the one surface having a larger transverse cross-sectional area than the other surface.
    Type: Grant
    Filed: March 29, 2022
    Date of Patent: June 4, 2024
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Man Gon Kim
  • Patent number: 12004296
    Abstract: A printed circuit board includes: an insulating member; a first wiring layer disposed in the insulating member, and including first and second pattern layers spaced apart from each other based on a thickness direction of the printed circuit board; and a second wiring layer disposed in the insulating member, and spaced apart from the first pattern layer over the first pattern layer based on the thickness direction. Based on the thickness direction, an insulation distance between the first pattern layer and the second pattern layer is smaller than an insulation distance between the first pattern layer and the second wiring layer, and each of the first and second pattern layers is thinner than the second wiring layer.
    Type: Grant
    Filed: April 4, 2022
    Date of Patent: June 4, 2024
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jin Uk Lee, Chi Won Hwang, Eun Sun Kim, Yong Wan Ji, Young Hun You
  • Patent number: 11979977
    Abstract: A method for manufacturing a circuit board including: providing at least one wiring base board, the wiring base board comprising a first conductor layer, an insulation layer, and an alloy layer which are stacked in order, wherein a solder paste layer is formed on a side of the alloy layer, a part of the alloy layer is exposed out of the solder paste layer to form a thermal conductive surface; providing a core layer; and pressing two wiring base boards on two opposite sides of the core layer to form a sealed heat dissipating chamber between the thermal conductive surfaces of the two wiring base boards. The present disclosure further provides a circuit board having a heat dissipation structure.
    Type: Grant
    Filed: August 31, 2019
    Date of Patent: May 7, 2024
    Assignees: QING DING PRECISION ELECTRONICS (HUAIAN) CO., LTD, Avary Holding (Shenzhen) Co., Limited.
    Inventors: Hsiao-Ting Hsu, Tao-Ming Liao, Ming-Jaan Ho, Xian-Qin Hu, Fu-Yun Shen
  • Patent number: 11963301
    Abstract: A printed circuit board includes: an insulating layer; a first circuit layer disposed on one surface of the insulating layer, and including a first circuit pattern and a first connection pad; and a surface treatment layer disposed on one surface of the first connection pad. The other surface of the first connection pad is covered by the insulating layer, and at least a portion of a side surface of the first connection pad is spaced apart from the insulating layer.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: April 16, 2024
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Seong Ho Choi, Tae Seok Kim
  • Patent number: 11963298
    Abstract: A printed wiring board includes a base insulating layer, a conductor layer formed on the base layer and including first and second pads, a solder resist layer formed on the base layer, covering the conductor layer and having first opening exposing the first pad and second opening exposing the second pad, a first bump formed on the first pad and including a base plating layer and a top plating layer, and a second bump formed on the second conductor pad and including a base plating layer and a top plating layer. The second opening has diameter smaller than diameter of the first opening, the second bump has diameter smaller than diameter of the first bump, the first pad has a first recess formed on the first pad, the second pad has a second recess formed on the second pad, and the first recess is larger than the second recess.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: April 16, 2024
    Assignee: IBIDEN CO., LTD.
    Inventors: Yoshiki Matsui, Atsushi Deguchi
  • Patent number: 11956895
    Abstract: The disclosure relates to a printed circuit board having at least two current-conducting layer plies, wherein the current-conducting layer plies extend in an axial direction of the printed circuit board and are arranged in succession in a thickness direction of the printed circuit board. A component fastened by THT is arranged on one side of the printed circuit board. At least one connecting element extends through the printed circuit board through a passage opening in the thickness direction. The current-conducting layer ply is adjacent to the component fastened by THT reaches as far as the connecting element and the current-conducting layer ply that is remote from the component fastened by THT is at a distance from the connecting element.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: April 9, 2024
    Assignee: ZF Friedrichshafen AG
    Inventor: Michael Sperber
  • Patent number: 11956896
    Abstract: A printed wiring board includes a first insulating layer, a conductor layer, and a second insulating layer. The conductor layer includes first and second circuits such that space is formed between the circuits, the first circuit has first and second side walls, the second circuit has third and fourth side walls such that the second wall faces the third wall, the first circuit has first, second and third portions, the second circuit has fourth, fifth and sixth portions such that the first and fourth portions, the second and fifth portions and the third and sixth portions face each other, the first circuit is formed such that the second wall of the second portion is recessed from the second wall of the first and third portions, and the first insulating layer has recess between the second and fifth portions such that the second insulating layer is filling the space and recess.
    Type: Grant
    Filed: February 21, 2022
    Date of Patent: April 9, 2024
    Assignee: IBIDEN CO., LTD.
    Inventors: Tomohiko Murata, Yoshiteru Hashimoto, Yoshiki Kawai, Hideyuki Goto
  • Patent number: 11943867
    Abstract: An electronic component includes a main body portion that has a first main surface having first and second sides, a second main surface opposite to the first main surface, a first side surface sharing the first side with the first main surface, and a second side surface sharing the second side with the first main surface, connection terminals that have electrical conductivity and that are arranged on the first main surface so as to be isolated from each other, and side-surface terminals that have electrical conductivity. The main body portion has side-surface grooves that are formed in the first and second side surfaces and that extend from the first main surface toward the second main surface. The side-surface terminals are provided on inner sides of the side-surface grooves and are each electrically connected to at least one of two end portions of the corresponding connection terminal.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: March 26, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Naofumi Takezono
  • Patent number: 11937373
    Abstract: One aspect of the instant application provides techniques to reduce the amount of crosstalk on single-ended signals in the pin field region of an integrated circuit device on a printed circuit board (PCB). The PCB can include a plurality of layers and an array of vias comprising a plurality of rows configured to route signals across layers. An inner layer of the PCB can include first and second signal traces positioned between first and second adjacent rows of the vias, the first signal trace positioned adjacent to the first row and the second signal trace positioned adjacent to the second row. The first signal trace can include at least one curved segment that curves around a substantial portion of a corresponding via in the first row such that separation between the first and second signal traces varies along the curved segment.
    Type: Grant
    Filed: March 8, 2022
    Date of Patent: March 19, 2024
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Melvin K. Benedict, Paul Danna, Chi Kim Sides, Wayne Vuong, Michael Chan
  • Patent number: 11930589
    Abstract: A printed wiring board includes a lower layer including conductor layers and insulating layers, a conductor layer formed on the outermost insulating layer in the lower layer, and a solder resist layer formed on the conductor layer such that the solder resist layer is covering the conductor layer on the outermost insulating layer, and a two-dimensional code structure formed on the lower layer and including the conductor layer and a portion of the solder resist layer such that the portion of the solder resist layer has openings forming exposed portions of the conductor layer and that the openings of the solder resist layer and the exposed portions of the conductor layer form the two-dimensional code structure. The conductor layer includes a portion corresponding to the two-dimensional code structure such that the portion of the conductor layer has a residual copper rate that allows the two-dimensional code structure to be read.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: March 12, 2024
    Assignee: IBIDEN CO., LTD.
    Inventor: Yoshihiko Hayashi
  • Patent number: 11917757
    Abstract: A circuit board includes a substrate including first and second sections with different thicknesses, a protective layer, and mounting electrodes. The substrate includes a step surface connecting a first principal surface of the first section and a first principal surface of the second section. The mounting electrodes are on the first principal surface corresponding to an element to be mounted. The protective layer is disposed over the first principal surface, the step surface, and the first principal surface. The separation distance between the mounting electrode and the step surface is greater than or equal to the terminal-to-terminal distance between the mounting electrode and the mounting electrode.
    Type: Grant
    Filed: October 7, 2021
    Date of Patent: February 27, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Hiroki Maegawa
  • Patent number: 11909158
    Abstract: Provided is a small-sized circuit board fixing structure capable of enabling a circuit board on a base to be easily replaced. A circuit board fixing structure configured to fix a circuit board onto a surface of a base includes a wire pattern formed on a surface of the circuit board, a first through hole penetrating from a front surface to a rear surface of the circuit board, a second through hole penetrating from a front surface to a rear surface of the base so as to communicate with the first through hole, an electrode penetratively inserted into the second through hole, and a fixing member engaged with the electrode mounted on the surface of the circuit board and configured to fix the circuit board to the base, in which when the fixing member and the electrode are engaged, the wire pattern and the electrode are electrically connected through the fixing member.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: February 20, 2024
    Assignee: HOYA CORPORATION
    Inventors: Hiroaki Watanabe, Katsumi Ashida
  • Patent number: 11910535
    Abstract: A printed circuit board stack structure includes a first printed circuit board, a second printed circuit board, and a filling glue layer. The first printed circuit board has at least one overflow groove, and includes first pads and a retaining wall surrounding the first pads. The second printed circuit board is disposed on the first printed circuit board, and includes second pads and conductive pillars located on some of the second pads. The conductive pillars are respectively connected to some of the first pads to electrically connect the second printed circuit board to the first printed circuit board. The filling glue layer fills between the first and the second printed circuit boards, and covers the first pads, the second pads, and the conductive pillars. The retaining wall blocks the filling glue layer so that a portion of the filling glue layer is accommodated in the overflow groove.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: February 20, 2024
    Assignee: Unimicron Technology Corp.
    Inventors: Ming-Hao Wu, Shih-Lian Cheng
  • Patent number: 11903121
    Abstract: A printed circuit board includes a reference plane embedded in a substrate and adjacent to the top surface of the substrate. The printed circuit board also includes a first signal net and a second signal net being in close proximity to each other and disposed within a specific region on the top surface of the substrate. An outermost insulating layer on the top surface of the substrate covers the substrate, the first signal net and the second signal net, and includes an opening to expose a portion of the second signal net. A conductive layer is disposed in the opening and on the outermost insulating layer corresponding to the specific region, such that the conductive layer overlaps with the first signal net. A fifth signal net is embedded in the substrate and between the reference plane and the outermost insulating layer.
    Type: Grant
    Filed: July 6, 2022
    Date of Patent: February 13, 2024
    Assignee: MediaTek Inc.
    Inventor: Nan-Jang Chen
  • Patent number: 11881333
    Abstract: Disclosed are a ground terminal and an electronic device. The ground terminal includes a core body, a first bonding layer, a second bonding layer, a metal support plate, a third bonding layer, a fourth bonding layer, and a metal work piece. The metal support plate is attached to a lower part of the core body. The metal work piece includes a contact layer, a side layer, an upper welding layer, a wrapping layer, and a lower welding layer. The contact layer is attached to an upper part of the core body, the side layer is located on one side of the core body, the upper welding layer is connected to the metal support plate, the wrapping layer wraps an end portion of the metal support plate, the upper and lower welding layers are connected to a top end of the wrapping layer and the metal support plate, respectively.
    Type: Grant
    Filed: May 22, 2023
    Date of Patent: January 23, 2024
    Assignee: Shenzhen Johan Material Technology Co., Ltd.
    Inventors: Mujiu Chen, Jingyun Liu, Qiao Chen
  • Patent number: 11877388
    Abstract: A component carrier includes a stack having at least one electrically conductive layer structure and/or at least one electrically insulating layer structure, a component embedded in the stack, and a functional film covering at least part of the component and having an inhomogeneous thickness distribution over at least part of a surface of the component.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: January 16, 2024
    Assignee: AT&SAustria Technologie & Systemtechnik AG
    Inventors: Imane Souli, Vanesa López Blanco, Erich Preiner, Martin Schrei
  • Patent number: 11871524
    Abstract: A component-incorporated substrate of multi-layer structure includes: a plurality of printed wiring base members that are batch-laminated via an adhesive layer, with the plurality of printed wiring base members including a resin base member that includes a wiring pattern on at least one surface thereof and a via connected to the wiring pattern; an opening disposed in at least one printed wiring base member that is sandwiched on both sides by other printed wiring base members of the plurality of printed wiring base members; and an electronic component disposed in the opening. At least part of the wiring pattern of the printed wiring base member where the opening is formed is disposed in a frame shape surrounding the opening, in a periphery of the opening.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: January 9, 2024
    Assignee: Fujikura Ltd.
    Inventor: Masahiro Okamoto
  • Patent number: 11871515
    Abstract: A wiring substrate includes an insulating layer having a through hole, a first conductor layer formed on a first surface of the insulating layer, a second conductor layer formed on a second surface of the insulating layer, an interlayer connection conductor formed in the through hole such that the interlayer connection conductor is connecting the first and second conductor layers, and a resin body formed in the through hole of the insulating layer such that a volume occupancy rate of the resin body is in a range of 30% to 55% in the through hole. The interlayer connection conductor is formed such that the interlayer connection conductor has a length in a range of 1000 ?m to 2000 ?m in a thickness direction of the insulating layer and that a volume occupancy rate of the interlayer connection conductor is in a range of 45% to 70% in the through hole.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: January 9, 2024
    Assignee: IBIDEN CO., LTD.
    Inventors: Yasuki Kimishima, Satoru Kawai