Patents Examined by Ishwarbhai B. Patel
  • Patent number: 12144125
    Abstract: A pressure-sensitive adhesive sheet-including wiring circuit board includes a wiring circuit board including a base insulating layer, a conductive layer disposed on a one-side surface in a thickness direction of the base insulating layer, and a cover insulating layer disposed on the one-side surface in the thickness direction of the base insulating layer so as to cover the conductive layer, and a pressure-sensitive adhesive sheet disposed on the surface of either one side or the other side in the thickness direction of the wiring circuit board.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: November 12, 2024
    Assignee: NITTO DENKO CORPORATION
    Inventors: Takahiro Takano, Takahiro Minatoya
  • Patent number: 12144106
    Abstract: An electronic device includes a circuit board, a shielding member, and a testing pin. The circuit board includes a grounding area. The shielding member is located on a side of the circuit board and includes a shielding layer and an insulating layer. The shielding layer is electrically connected to the grounding area. The insulating layer is located on a side of the shielding layer away from the circuit board. The testing pin is disposed on the circuit board and electrically connected to the shielding layer.
    Type: Grant
    Filed: May 6, 2022
    Date of Patent: November 12, 2024
    Assignee: TPK Auto Tech (Xiamen) Limited
    Inventors: Li Hua Wei, Ming Hsiang Lin, Shih Hao Chen, Cai Jin Ye
  • Patent number: 12144116
    Abstract: A printed circuit board according to an embodiment includes a first insulating layer, a second insulating layer disposed on the first insulating layer and including a cavity; and a pad disposed on the first insulating layer and having an upper surface exposed through the cavity; wherein the cavity includes a first part including a first inner wall; and a second part including a second inner wall under the first part; and wherein an inclination angle of the first inner wall is different from an inclination angle of the second inner wall.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: November 12, 2024
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Jong Bae Shin, Soo Min Lee, Jae Hun Jeong
  • Patent number: 12120815
    Abstract: A multilayer substrate includes an insulator that includes a first region and a second region that is thinner than the first region, and a first signal line and a second signal line that are structured to extend across the first region and the second region. In a region in which the first signal line and the second signal line face each other, a line width of the first signal line and a line width of the second signal line are smaller in the second region than in the first region, and a distance between the first signal line and the second signal line is smaller in the second region than in the first region.
    Type: Grant
    Filed: June 13, 2023
    Date of Patent: October 15, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Tomohiro Nagai
  • Patent number: 12108530
    Abstract: A circuit board structure includes a circuit substrate, a first circuit layer, and a second circuit layer. The circuit substrate has a surface and includes at least one conductive structure and at least one patterned circuit layer. The conductive structure is electrically connected to the patterned circuit layer, and an upper surface of the conductive structure is aligned with the surface. The first circuit layer is directly disposed on the surface of the circuit substrate and electrically connected to the conductive structure. A line width of the first circuit layer is less than or equal to 1/4 of a line width of the patterned circuit layer. The second circuit layer is directly disposed on the first circuit layer and electrically connected to the first circuit layer.
    Type: Grant
    Filed: August 30, 2022
    Date of Patent: October 1, 2024
    Assignee: Unimicron Technology Corp.
    Inventors: Kuang-Ching Fan, Chih-Peng Hsieh, Cheng-Hsiung Wang
  • Patent number: 12108532
    Abstract: A printed circuit board with an embedded bridge includes: a first connection structure including a first insulating film; a bridge disposed on the first connection structure and having one surface, in contact with the first insulating film; and a second connection structure disposed on the first connection structure, and including a second insulating film. The second insulating film covers at least a portion of the other surface of the bridge.
    Type: Grant
    Filed: February 1, 2023
    Date of Patent: October 1, 2024
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Moon Seok Heo, Hyung Ki Lee
  • Patent number: 12101879
    Abstract: A flexible printed circuit board (FPCB), which is applied to various electronic display devices, may include a base, a first metal layer and a second metal layer on both surfaces of the base, a first plating layer on the first metal layer, a second plating layer on the second metal layer, and a first insulating pattern and a second insulating pattern respectively disposed on some region of the first plating layer and the second plating layer, wherein the first plating layer and the second plating layer may have different thicknesses.
    Type: Grant
    Filed: July 3, 2023
    Date of Patent: September 24, 2024
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Jun Young Lim, Woong Sik Kim, Hyung Kyu Yoon
  • Patent number: 12096556
    Abstract: A interconnect substrate includes an insulating layer including an organic resin layer and a plurality of embedded portions that are embedded in the organic resin layer and exposed at an upper surface of the organic resin layer, and an interconnect layer in contact with the upper surface of the organic resin layer and an upper surface of the embedded portions, wherein the embedded portions are made of an oxide, nitride, or oxynitride of inorganic material, and wherein the upper surface of the organic resin layer is partially exposed in areas where the interconnect layer is not formed on the insulating layer.
    Type: Grant
    Filed: June 2, 2022
    Date of Patent: September 17, 2024
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Yuta Yamazaki
  • Patent number: 12096555
    Abstract: A component carrier includes a first stack with an electrically insulating layer structure and an electrically conductive layer structure with a first density of trace structures and a second density of first connection structures, a second stack with a second electrically insulating layer structure and a second electrically conductive layer structure with a third density of second trace structures and a fourth density of second connection structures. A first component is applied to the first stack and a second component is embedded in the second stack. The first connection structures are respectively connected to the second connection structures. The first density of first trace structures is lower than the third density of second trace structures. The first stack and the second stack are connected with each other by the first connection structures and by the second connection structures. The first component is connected to the second component.
    Type: Grant
    Filed: March 16, 2022
    Date of Patent: September 17, 2024
    Assignee: AT&S Austria Technologie & Systemtechnik AG
    Inventors: Markus Leitgeb, Gernot Grober
  • Patent number: 12089326
    Abstract: A double-sided flexible circuit board includes a flexible substrate, through circuit lines, first circuit lines and second circuit lines. The first circuit lines are formed on a top surface of the flexible substrate and each includes a first segment, a bent segment and a second segment. One end of the first segment is connected to a first connection end of one of the through circuit lines. Both ends of the bent segment are connected to the other end of the first segment and one end of the second segment, respectively. A second distance between the adjacent second segments is greater than a first distance between the adjacent first segments. The second circuit lines are formed on a bottom surface of the flexible substrate and each is connected to a second connection end of one of the through circuit lines.
    Type: Grant
    Filed: May 11, 2022
    Date of Patent: September 10, 2024
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Yin-Chen Lin, Hui-Yu Huang, Chih-Ming Peng, Chun-Te Lee
  • Patent number: 12089347
    Abstract: A circuit board, comprising a multi-layer circuit board, a first conductive circuit, a first circuit layer, an adhesion promoter layer, a second conductive circuit, and a second circuit layer. The multi-layer circuit board comprises an inner circuit and an opening. The opening exposes the inner circuit. The first conductive circuit is disposed in the opening and on the inner circuit. The first circuit layer is disposed on the first conductive circuit in the opening and lower than the depth of the opening. The adhesion promoter layer is disposed in the opening and on the surface of the multi-layer circuit board and connected to the first conductive circuit. The second conductive circuit is disposed on the adhesion promoter layer and on the first circuit layer in the opening. The second circuit layer is disposed on the second conductive circuit in the opening and on the second conductive circuit.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: September 10, 2024
    Assignee: UNIMICRON TECHNOLOGY CORP.
    Inventors: Chun Yi Kuo, Jia Hao Liang, Ching Ku Lin
  • Patent number: 12075566
    Abstract: An electronic device is provided. The electronic device includes: a substrate, wherein the substrate has a normal direction; a first bonding pad and a second bonding pad disposed side by side on the substrate. The first bonding pad includes a first conductive layer and a second conductive layer, and the first conductive layer is adjacent to the second conductive layer. The second bonding pad includes a third conductive layer, the third conductive layer is adjacent to the second conductive layer, and in the normal direction, a distance between a bottom surface of the third conductive layer and the substrate is different than a distance between a bottom surface of the second conductive layer and the substrate. Viewed from the normal direction of the substrate, at least part of the second conductive layer is between the first conductive layer and the third conductive layer.
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: August 27, 2024
    Assignee: INNOLUX CORPORATION
    Inventors: Yu-Ting Liu, Yeong-E Chen, Chean Kee
  • Patent number: 12058814
    Abstract: A power module and a manufacturing method thereof are disclosed. The power module includes a first board, a magnetic component, a second board and a power device. The first board includes a conductive component disposed between a first side and a second side opposite to each other. The magnetic component is disposed between the first side and the second side and includes a magnetic core and a winding. A first conductive terminal and a second conductive terminal are led out on the first side and the second side, respectively. The second board is disposed on the first board and includes a third side and a fourth side opposite to each other. The fourth side faces the first side. The power device is disposed on the third side of the second board and electrically connected to the first board.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: August 6, 2024
    Assignee: DELTA ELECTRONICS (SHANGHAI) CO., LTD.
    Inventors: Shouyu Hong, Jinping Zhou, Min Zhou, Xiaoni Xin, Pengkai Ji, Kai Lu, Le Liang, Zhenqing Zhao
  • Patent number: 12052819
    Abstract: A printed wiring board includes a base insulating layer, a conductor layer formed on the base layer and including pads, a solder resist layer formed on the base layer such that the solder resist layer is covering the conductor layer and has openings exposing the pads, and plating bumps formed on the pads such that each plating bump includes a base plating layer formed in a respective one of the openings, an intermediate layer formed on the base plating layer, and a top plating layer formed on the intermediate layer. The plating bumps are formed such that the base plating layer has a side surface including a portion protruding from the solder resist layer, that the intermediate layer has a thickness in a range of 2.7 to 7.0 ?m, and that the top plating layer has a hemispherical shape and is covering only an upper surface of the intermediate layer.
    Type: Grant
    Filed: March 29, 2022
    Date of Patent: July 30, 2024
    Assignee: IBIDEN CO., LTD.
    Inventor: Tomohiro Kobayashi
  • Patent number: 12048089
    Abstract: A component carrier for carrying at least one electronic component includes (a) a plurality of electrically conductive layers; (b) a plurality of electrically insulating layers; and (c) a thermoplastic structure. The electrically conductive layers, the electrically insulating layers, and the thermoplastic structure form a laminate. Further, a method for manufacturing such a component carrier and an electronic apparatus including such a component carrier are provided.
    Type: Grant
    Filed: October 10, 2022
    Date of Patent: July 23, 2024
    Assignee: AT&SAustria Technologie & Systemtechnik
    Inventor: Thomas Krivec
  • Patent number: 12034260
    Abstract: A connection body, a method for manufacturing a connection body, and a connection method which can secure conduction reliability by trapping conductive particles even when the bump size is minimized. In a connection body in which a first component having a first electrode and a second component having a second electrode are connected to each other via a filler-containing film having a filler-aligned layer in which independent fillers are aligned in a binder resin layer, the maximum effective connection portion area where the first electrode and the second electrode face each other is 4,000 ?m2 or less and a ratio of the effective connection portion area to a particle area on the connection portion projection plane is 3 or more.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: July 9, 2024
    Assignee: DEXERIALS CORPORATION
    Inventors: Ryota Aizaki, Kosuke Asaba
  • Patent number: 12035466
    Abstract: Printed circuit boards (PCB) used to mechanically and electrically connect electrical components within an electronic device. Thin printed circuit boards (PCB) may be desirable to manufacturers and users of electronic devices. Accordingly, a process for manufacturing a printed circuit board may involve manufacturing a thin bilayer dielectric. The process may involve applying a first non-conductive layer to a metal substrate, and curing the first non-conductive layer to a C-stage resin layer that is fully cross-linked layer in a clean environment. In turn, a B-stage layer that is partially cured may be applied to the C-stage resin layer. Using a hot press, one or more metal traces may be pressed onto the B-stage layer. The B-stage resin layer may be fully cross-linked and integrated with the C-stage resin layer after lamination of the one or more metal traces and the B-stage resin layer.
    Type: Grant
    Filed: April 21, 2021
    Date of Patent: July 9, 2024
    Assignee: Apple Inc.
    Inventors: Mark J. Beesley, Meng Chi Lee, Nima Shahidi, Hao Shi, Quan Qi
  • Patent number: 12035473
    Abstract: A circuit assembly includes a flexible card having a main panel and an extension panel foldably connected along a fold line and a card circuit disposed on the flexible card and having one or more contact points disposed proximate the fold line, and a circuit board having one or more electrical contacts formed on a surface of the circuit board. The flexible card and the circuit board can be disposed in face-to-face contact with each contact point of the card circuit is in registry with a respective electrical contact of the circuit board, with the extension panel folded at the fold line over the circuit board. The assembly includes a clip disposed over the folded extension panel and main panel to apply a sandwiching force to secure the circuit board and the card circuit in electrical contact.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: July 9, 2024
    Assignee: WestRock MWV, LLC
    Inventors: Ronald Binshtok, Carly J. Dehenau, James S. Shortt, Trisha Massenzo
  • Patent number: 12028973
    Abstract: A printed circuit board includes a first insulating layer, a metal layer disposed on one surface of the first insulating layer, a first circuit layer disposed inside the first insulating layer and having one surface exposed to the one surface of the first insulating layer so as to be in contact with one surface of the metal layer, a second circuit layer in contact with the other surface of the metal layer, and a second insulating layer disposed on the one surface of the first insulating layer to cover the metal layer and the second circuit layer. The first and second circuit layers respectively include a metal different from the metal layer.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: July 2, 2024
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Chan Jin Park, Young Ook Cho, Hyun Seok Yang, Ki Joo Sim, Won Seok Lee, Mi Jeong Jeon
  • Patent number: 12022612
    Abstract: The present disclosure provides a circuit board and its manufacturing method. The circuit board includes a first circuit layer, a first conductive post, and a second circuit layer. The first circuit layer includes a first pad and a first seed layer covering a sidewall of the first pad. The first conductive post is on the first pad and directly connected to the first pad. The second circuit layer includes a second pad and a second seed layer covering a sidewall of the second pad. The second pad is on a first connecting end of the first conductive post. The first connecting end is embedded in the second pad, and the second pad is connected to and directly contacts the first connecting end. The first seed layer and the second seed layer do not extend on a sidewall of the first conductive post.
    Type: Grant
    Filed: May 5, 2022
    Date of Patent: June 25, 2024
    Assignee: Unimicron Technology Corp.
    Inventor: Chun-Hung Kuo