Patents Examined by Ishwarbhai B. Patel
  • Patent number: 12267950
    Abstract: A flexible printed wiring board according to an aspect includes a base film, a conductive pattern disposed on one surface of the base film, and an extra length absorbing portion protruding from the base film and disposed in a direction of a plane, the extra length absorbing portion including a pattern connected portion connected to the conductive pattern, a coupling portion having a first linear wiring portion, a first arcuate wiring portion, and a second linear wiring portion coupled in this order continuously from the pattern connected portion, and a connecting terminal connected to the coupling portion, the pattern connected portion and the connecting terminal being opposite to each other in a direction in which the extra length absorbing portion protrudes.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: April 1, 2025
    Assignees: SUMITOMO ELECTRIC PRINTED CIRCUITS, INC., SUMITOMO ELECTRIC INDUSTRIES, LTD., SUMITOMO WIRING SYSTEMS, LTD., AUTONETWORKS TECHNOLOGIES, LTD.
    Inventors: Shuji Hahakura, Shinichi Takase, Yoshifumi Uchita, Hideo Takahashi
  • Patent number: 12266598
    Abstract: An enhanced integrated circuit interconnect package, method and multiple-layer integrated circuit laminate structure enable increased routing density per layer and maintains signal integrity performance. A differential signal via pair of vertical interconnect vias provide differential signaling. The vias of the differential signal via pair are positioned closely spaced together with each via offset from a center axis of an associated LGA contact, minimizing space between the differential signal vias and maintaining signal integrity performance, and providing increased available wiring signal channel.
    Type: Grant
    Filed: October 24, 2022
    Date of Patent: April 1, 2025
    Assignee: International Business Machines Corporation
    Inventors: Francesco Preda, Sungjun Chun, Jose A. Hejase, Junyan Tang, Pavel Roy Paladhi, Nam Huu Pham, Wiren Dale Becker, Daniel Mark Dreps
  • Patent number: 12256500
    Abstract: A circuit board includes: a base substrate in which a protective layer formation region is defined; a wiring pattern which is formed on the base substrate and which has at least a portion formed in the protective layer formation region; a protective layer fixed onto the protective layer formation region and formed of a protective material; and a bleed prevention pattern formed on the base substrate so as to prevent the protective material from flowing beyond the protective layer formation region when the protective layer is formed.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: March 18, 2025
    Assignee: STEMCO CO., LTD.
    Inventors: Jin Han Lee, Sung Jin Lee, Jin Ho Kim
  • Patent number: 12255000
    Abstract: A compound superconducting twisted wire includes compound superconducting strands being twisted to form a twisted structure, in which each of the compound superconducting strands includes a compound superconductor part, a reinforcing part and a stabilizing part. The compound superconductor part includes compound superconducting filaments and a first matrix, the compound superconducting filaments each including a compound superconducting phase. The reinforcing part is disposed on an outer circumferential side of the compound superconductor part and includes reinforcing filaments and a second matrix. The stabilizing part is disposed on at least one side of an inner circumferential side and an outer circumferential side of the reinforcing part. A volume ratio of the reinforcing part relative to the compound superconducting strand is larger than a volume ratio of the compound superconductor part relative to the compound superconducting strand.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: March 18, 2025
    Assignees: FURUKAWA ELECTRIC CO., LTD., TOHOKU UNIVERSITY, TOKAI UNIVERSITY EDUCATIONAL SYSTEM
    Inventors: Masahiro Sugimoto, Hirokazu Tsubouchi, Daisuke Asami, Hideki Ii, Satoshi Awaji, Hidetoshi Oguro
  • Patent number: 12243813
    Abstract: Provided is a connection structure for a semiconductor package which includes: a first passivation layer having an opening; a first conductive pattern that penetrates the first passivation layer and protrudes upwardly from the first passivation layer; a second passivation layer on the first passivation layer and covering the first conductive pattern; a second conductive pattern on the second passivation layer and electrically connected to the first conductive pattern; a third passivation layer on the second passivation layer and covering the second conductive pattern; and an external terminal in the opening and electrically connected to the first conductive pattern, wherein the first conductive pattern is thicker than the second conductive pattern.
    Type: Grant
    Filed: October 10, 2023
    Date of Patent: March 4, 2025
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jongyoun Kim
  • Patent number: 12245373
    Abstract: A printed circuit board is provided. The printed circuit board includes a substrate, an electrically conductive pattern layer, and a thermally conductive ink layer. The substrate includes a first surface. The electrically conductive pattern layer is located on the first surface and includes a contact portion and a wire portion. The thermally conductive ink layer covers the wire portion and exposes the contact portion. The thermally conductive ink layer includes a thermally conductive powder and a colloidal adhesive, where a weight percentage of the thermally conductive powder is less than 10%, and a weight percentage of the colloidal adhesive is higher than 80%. An electronic device including the printed circuit board is further provided.
    Type: Grant
    Filed: February 3, 2022
    Date of Patent: March 4, 2025
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Ping-Han Tsou, Li-Chien Wan
  • Patent number: 12238855
    Abstract: A printed circuit board (PCB) includes first and second signal pads and a guard trace formed on a surface of the PCB. The first and second signal pads are for connecting to signal contacts of a high-speed data communication interface. The guard trace is located between the first signal pad and the second signal pad. The PCB further includes first, second, and third ground vias that couple the guard trace to a ground plane of the PCB. The first ground via is located at a first end of the guard trace. The second ground via is located at a second end of the guard trace. The third ground via is located between the first via and the second via.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: February 25, 2025
    Assignee: Dell Products L.P.
    Inventors: Vijender Kumar, Malikarjun Vasa, Bhyrav Mutnury
  • Patent number: 12238861
    Abstract: A composite printed wiring board includes a first printed wiring board, a second printed wiring board, an intermediate plate, a first bonding layer, and a second bonding layer. The intermediate plate is provided to surround a space. The first printed wiring board closes one side of the space and is bonded to the intermediate plate. The second printed wiring board closes the other side of the space and is bonded to the intermediate plate. At least any of the first printed wiring board and the second printed wiring board has a through hole. A cavity is provided that is the space surrounded by the first printed wiring board, the second printed wiring board, the intermediate plate, the first bonding layer, and the second bonding layer. The through hole in communication with the cavity.
    Type: Grant
    Filed: September 14, 2022
    Date of Patent: February 25, 2025
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Tatsuya Sakamoto, Kenjiro Takanishi, Hitoshi Arai, Hiroshi Goto, Akihito Hirai
  • Patent number: 12232257
    Abstract: A wiring substrate includes an insulating layer, a conductor layer formed on the insulating layer and including a conductor pad having a rectangular planar shape, and a solder resist layer formed on the insulating layer such that the solder resist layer is covering the conductor layer formed on the insulating layer. The solder resist layer has an opening formed such that the opening is exposing 50% or more of an area of a surface of the conductor pad on the opposite side with respect to the insulating layer and exposing a side surface and the surface of the conductor pad at side portions of a peripheral edge of the conductor pad and that the solder resist layer is covering the side surface and the surface of the conductor pad at one or more of corner portions of the peripheral edge of the conductor pad.
    Type: Grant
    Filed: November 24, 2021
    Date of Patent: February 18, 2025
    Assignee: IBIDEN CO., LTD.
    Inventors: Shunsuke Sakai, Shuto Iwata, Ikuya Terauchi, Takahiro Yamada
  • Patent number: 12225661
    Abstract: A multilayer substrate includes an insulator that includes a first region and a second region that is thinner than the first region, and a first signal line and a second signal line that are structured to extend across the first region and the second region. In a region in which the first signal line and the second signal line face each other, a line width of the first signal line and a line width of the second signal line are smaller in the second region than in the first region, and a distance between the first signal line and the second signal line is smaller in the second region than in the first region.
    Type: Grant
    Filed: June 13, 2023
    Date of Patent: February 11, 2025
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Tomohiro Nagai
  • Patent number: 12219694
    Abstract: A battery wiring module includes a plurality of connecting members to be connected to electrode terminals and a flexible printed circuit board having a plurality of voltage detection lines for detecting the voltages of a plurality of power storage elements via the plurality of connecting members, at least one of the plurality of voltage detection lines being constituted to include a front surface wiring and a back surface wiring respectively formed on a front surface and a back surface of the flexible printed circuit board, and a front-back conduction part passing through the flexible printed circuit board in the plate thickness direction and connecting the front surface wiring and the back surface wiring, and the resistance value per unit length of the front-back conduction part being less than or equal to the maximum resistance value per unit length of the front surface wiring and the back surface wiring.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: February 4, 2025
    Assignees: AUTONETWORKS TECHNOLOGIES, LTD., SUMITOMO WIRING SYSTEMS, LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Hideo Takahashi, Shinichi Takase
  • Patent number: 12213248
    Abstract: A printed wiring board includes resin insulating layers, and conductor layers laminated on the resin insulating layers, respectively. The conductor layers includes a conductor layer including a conductor circuit formed such that the conductor circuit has recesses each having a depth of 2.0 ?m or more and a bottom whose diameter is larger than a diameter of an opening part of a respective one of the recesses.
    Type: Grant
    Filed: May 19, 2022
    Date of Patent: January 28, 2025
    Assignee: IBIDEN CO., LTD.
    Inventors: Shigeto Iyoda, Tomoyuki Ikeda
  • Patent number: 12213254
    Abstract: A multi-layer printed circuit board includes a base-layer metal, multiple middle metal layers and a top-layer metal. The middle metal layers are stacked on the base-layer metal sequentially. The top-layer metal is disposed on the middle metal layers. The base-layer metal, each middle metal layer and the top-layer metal are formed with multiple through holes respectively. Part of the middle metal layers are separately formed with multiple hole groups corresponding to the through holes. Each hole group includes multiple passing holes. The passing holes jointly surround a corresponding one of the through holes to form multiple connecting channels. Therefore, the multi-layer printed circuit board may reduce the cooling speed of the through holes to avoid an excessively low temperature of a pad to affect the soldering efficiency with keeping the high-frequency transmission and the signal isolation.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: January 28, 2025
    Assignee: JESS-LINK PRODUCTS CO., LTD.
    Inventor: Yu-Liang Liu
  • Patent number: 12207399
    Abstract: A component carrier has a stack including a plurality of electrically insulating layer structures and at least one electrically conductive layer structure, wherein two of the at least two electrically insulating layer structures form a dielectric double layer made of two different materials; a through-hole extending through the double dielectric layer; and an electrically conductive material filling at least a part of the through-hole. A method of manufacturing a component carrier is also disclosed.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: January 21, 2025
    Assignee: AT&S (Chongqing) Company Limited
    Inventor: Jeesoo Mok
  • Patent number: 12207402
    Abstract: A printed circuit board for transmitting electrical energy and for signal transmission includes electrical conductor tracks coupled to the printed circuit board wherein the electrical conductor tracks include a first electrical conductor track with a superconducting material. The first electrical conductor track is designed to provide electrical energy directly to a power electronics system. The electrical conductor tracks include a second electrical conductor track which is designed to provide a signal transmission to a signal electronics system. A system is disclosed having such a printed circuit board.
    Type: Grant
    Filed: January 12, 2022
    Date of Patent: January 21, 2025
    Assignee: Airbus Defence and Space GmbH
    Inventors: Stephan Friedl, Florian Kapaun
  • Patent number: 12207404
    Abstract: A circuit board may include an insulating layer; a circuit pattern disposed above the top surface of or below the bottom surface of the insulating layer; and a buffer layer disposed between the insulating layer and the circuit pattern, the buffer layer comprising carbon atoms, nitrogen atoms, oxygen atoms, silicon atoms, sulfur atoms, and metal atoms. The ratio of the carbon atoms to the metal atoms ((carbon atom/copper atom)*100) is within a range of 5-7; the ratio of the nitrogen atoms to the metal atoms ((nitrogen atom/copper atom)*100) is within a range of 1.5-7; the ratio of the oxygen atoms to the metal atoms ((oxygen atom/copper atom)*100) is within a range of 1.1-1.9; and the ratio of the silicon atoms to the metal atoms ((silicon atom/copper atom)*100) is within a range of 0.5-0.9; and the ratio of the sulfur atoms to the metal atoms ((sulfur atom/copper atom)*100) is within a range of 0.5-1.5.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: January 21, 2025
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Yong Suk Kim, Dong Hwa Lee
  • Patent number: 12200853
    Abstract: A heat sink component can include a body including a thermally conductive material that is electrically non-conductive, a lower conductive layer formed over a bottom surface of the body and electrically connected with the ground plane layer, and an upper conductive layer formed over a top surface of the body. The heat sink component can have a length in an X-direction that is parallel with the top surface of the body and a thickness in a direction perpendicular to the top surface. A ratio of the length to the thickness can be greater than about 7.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: January 14, 2025
    Assignee: KYOCERA AVX Components Corporation
    Inventors: Cory Nelson, Jeff Borgman, Marianne Berolini
  • Patent number: 12193145
    Abstract: A substrate for mounting electronic element includes: a first substrate including a first surface and a second surface opposite to the first surface; a second substrate including a third surface and a fourth surface opposite to the third surface; and heat dissipation bodies each including a fifth surface and a sixth surface opposite to the fifth surface. The first substrate includes at least one mounting portion for at least one electronic element at the first surface. Heat conduction of the heat dissipation bodies in a direction perpendicular to a longitudinal direction of the at least one mounting portion and perpendicular to a direction along opposite sides of the second substrate is greater than heat conduction of the heat dissipation bodies in the longitudinal direction of the at least one mounting portion and in the direction along opposite sides of the second substrate in a transparent plan view of the substrate.
    Type: Grant
    Filed: January 20, 2023
    Date of Patent: January 7, 2025
    Assignee: KYOCERA Corporation
    Inventors: Yukio Morita, Noboru Kitazumi, Yousuke Moriyama
  • Patent number: 12187010
    Abstract: A glass structure includes a glass plate; a connecting member placed on one surface of the glass plate, and is electrically connected to a conductor placed on the glass plate or placed in the vicinity of the glass plate, the connecting member including a connecting portion at one end thereof and a power supply portion at the other end thereof, and a portion other than the connecting portion and the power supply portion are covered by a resin portion; wherein the glass structure is adhered to a predetermined portion by an adhesive; and the glass structure including a base layer extending as a strip along the edge of the glass plate is placed on the surface of the glass plate and the surface of the resin portion of the connecting member, wherein the base layer including a resin primer layer, a glass primer layer and a sealant layer.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: January 7, 2025
    Assignee: AGC INC.
    Inventors: Masayuki Sase, Akira Yamauchi
  • Patent number: 12193156
    Abstract: A wiring substrate includes a first insulating layer, a conductor layer formed on the first insulating layer, a second insulating layer formed on the first insulating layer such that the second insulating layer is covering the conductor layer, and a coating film formed on a surface of the conductor layer such that the coating film is adhering the conductor layer and the second insulating layer. The conductor layer includes a conductor pad and a wiring pattern, and the conductor pad of the conductor layer has a mounting surface including a first region and a component mounting region formed such that the second insulating layer has a through hole exposing the component mounting region and that the first region is covered by the second insulating layer and roughened to have a surface roughness higher than a first surface roughness of a surface of the wiring pattern facing the second insulating layer.
    Type: Grant
    Filed: April 27, 2022
    Date of Patent: January 7, 2025
    Assignee: IBIDEN CO., LTD.
    Inventors: Tomoyuki Ikeda, Kentaro Wada