Patents Examined by Ishwarbhai B. Patel
  • Patent number: 12048089
    Abstract: A component carrier for carrying at least one electronic component includes (a) a plurality of electrically conductive layers; (b) a plurality of electrically insulating layers; and (c) a thermoplastic structure. The electrically conductive layers, the electrically insulating layers, and the thermoplastic structure form a laminate. Further, a method for manufacturing such a component carrier and an electronic apparatus including such a component carrier are provided.
    Type: Grant
    Filed: October 10, 2022
    Date of Patent: July 23, 2024
    Assignee: AT&SAustria Technologie & Systemtechnik
    Inventor: Thomas Krivec
  • Patent number: 12034260
    Abstract: A connection body, a method for manufacturing a connection body, and a connection method which can secure conduction reliability by trapping conductive particles even when the bump size is minimized. In a connection body in which a first component having a first electrode and a second component having a second electrode are connected to each other via a filler-containing film having a filler-aligned layer in which independent fillers are aligned in a binder resin layer, the maximum effective connection portion area where the first electrode and the second electrode face each other is 4,000 ?m2 or less and a ratio of the effective connection portion area to a particle area on the connection portion projection plane is 3 or more.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: July 9, 2024
    Assignee: DEXERIALS CORPORATION
    Inventors: Ryota Aizaki, Kosuke Asaba
  • Patent number: 12035466
    Abstract: Printed circuit boards (PCB) used to mechanically and electrically connect electrical components within an electronic device. Thin printed circuit boards (PCB) may be desirable to manufacturers and users of electronic devices. Accordingly, a process for manufacturing a printed circuit board may involve manufacturing a thin bilayer dielectric. The process may involve applying a first non-conductive layer to a metal substrate, and curing the first non-conductive layer to a C-stage resin layer that is fully cross-linked layer in a clean environment. In turn, a B-stage layer that is partially cured may be applied to the C-stage resin layer. Using a hot press, one or more metal traces may be pressed onto the B-stage layer. The B-stage resin layer may be fully cross-linked and integrated with the C-stage resin layer after lamination of the one or more metal traces and the B-stage resin layer.
    Type: Grant
    Filed: April 21, 2021
    Date of Patent: July 9, 2024
    Assignee: Apple Inc.
    Inventors: Mark J. Beesley, Meng Chi Lee, Nima Shahidi, Hao Shi, Quan Qi
  • Patent number: 12035473
    Abstract: A circuit assembly includes a flexible card having a main panel and an extension panel foldably connected along a fold line and a card circuit disposed on the flexible card and having one or more contact points disposed proximate the fold line, and a circuit board having one or more electrical contacts formed on a surface of the circuit board. The flexible card and the circuit board can be disposed in face-to-face contact with each contact point of the card circuit is in registry with a respective electrical contact of the circuit board, with the extension panel folded at the fold line over the circuit board. The assembly includes a clip disposed over the folded extension panel and main panel to apply a sandwiching force to secure the circuit board and the card circuit in electrical contact.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: July 9, 2024
    Assignee: WestRock MWV, LLC
    Inventors: Ronald Binshtok, Carly J. Dehenau, James S. Shortt, Trisha Massenzo
  • Patent number: 12028973
    Abstract: A printed circuit board includes a first insulating layer, a metal layer disposed on one surface of the first insulating layer, a first circuit layer disposed inside the first insulating layer and having one surface exposed to the one surface of the first insulating layer so as to be in contact with one surface of the metal layer, a second circuit layer in contact with the other surface of the metal layer, and a second insulating layer disposed on the one surface of the first insulating layer to cover the metal layer and the second circuit layer. The first and second circuit layers respectively include a metal different from the metal layer.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: July 2, 2024
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Chan Jin Park, Young Ook Cho, Hyun Seok Yang, Ki Joo Sim, Won Seok Lee, Mi Jeong Jeon
  • Patent number: 12022612
    Abstract: The present disclosure provides a circuit board and its manufacturing method. The circuit board includes a first circuit layer, a first conductive post, and a second circuit layer. The first circuit layer includes a first pad and a first seed layer covering a sidewall of the first pad. The first conductive post is on the first pad and directly connected to the first pad. The second circuit layer includes a second pad and a second seed layer covering a sidewall of the second pad. The second pad is on a first connecting end of the first conductive post. The first connecting end is embedded in the second pad, and the second pad is connected to and directly contacts the first connecting end. The first seed layer and the second seed layer do not extend on a sidewall of the first conductive post.
    Type: Grant
    Filed: May 5, 2022
    Date of Patent: June 25, 2024
    Assignee: Unimicron Technology Corp.
    Inventor: Chun-Hung Kuo
  • Patent number: 12022613
    Abstract: A printed circuit board includes: a first insulating layer having a recess portion in one surface of the first insulating layer; a first circuit pattern embedded in the first insulating layer and being in contact with a lower surface of the recess portion; a second insulating layer disposed on the one surface of the first insulating layer to be disposed in at least a portion of the recess portion; and a via penetrating through at least a portion of the second insulating layer, disposed in the recess portion, and connected to the first circuit pattern.
    Type: Grant
    Filed: May 18, 2022
    Date of Patent: June 25, 2024
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Yong Wan Ji, Jin Uk Lee, Eun Sun Kim, Young Hun You
  • Patent number: 12010794
    Abstract: A printed wiring board includes a base insulating layer, a conductor layer formed on the base insulating layer and including conductor pads, a solder resist layer formed on the base insulating layer such that the solder resist layer is covering the conductor layer and having openings exposing the conductor pads, respectively, and plating bumps formed on the conductor pads such that each of the plating bumps includes a base plating layer formed in a respective one of the openings of the solder resist layer, and a top plating layer formed on the base plating layer. The plating bumps are formed such that the base plating layer has an upper surface and a side surface including a portion protruding from the solder resist layer and having a rough surface and that the top plating layer has a hemispherical shape and is covering only the upper surface of the base plating layer.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: June 11, 2024
    Assignee: IBIDEN CO., LTD.
    Inventor: Satoru Kawai
  • Patent number: 12004296
    Abstract: A printed circuit board includes: an insulating member; a first wiring layer disposed in the insulating member, and including first and second pattern layers spaced apart from each other based on a thickness direction of the printed circuit board; and a second wiring layer disposed in the insulating member, and spaced apart from the first pattern layer over the first pattern layer based on the thickness direction. Based on the thickness direction, an insulation distance between the first pattern layer and the second pattern layer is smaller than an insulation distance between the first pattern layer and the second wiring layer, and each of the first and second pattern layers is thinner than the second wiring layer.
    Type: Grant
    Filed: April 4, 2022
    Date of Patent: June 4, 2024
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jin Uk Lee, Chi Won Hwang, Eun Sun Kim, Yong Wan Ji, Young Hun You
  • Patent number: 12004292
    Abstract: A printed circuit board includes: a first multilayer substrate including first and second vias adjacent to each other in a stacking direction of the printed circuit board; a second multilayer substrate disposed on the first multilayer substrate in the stacking direction and including third and fourth vias adjacent to each other in the stacking direction; and an adhesive layer connecting respective one surfaces of the first and second multilayer substrates to each other. Each of the first to fourth vias has one surface and the other surface facing the one surface, the one surface being closer to the adhesive layer than the other surface, and the one surface having a larger transverse cross-sectional area than the other surface.
    Type: Grant
    Filed: March 29, 2022
    Date of Patent: June 4, 2024
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Man Gon Kim
  • Patent number: 11999001
    Abstract: A microelectronic assembly includes a first substrate having a surface and a first conductive element and a second substrate having a surface and a second conductive element. The assembly further includes an electrically conductive alloy mass joined to the first and second conductive elements. First and second materials of the alloy mass each have a melting point lower than a melting point of the alloy. A concentration of the first material varies in concentration from a relatively higher amount at a location disposed toward the first conductive element to a relatively lower amount toward the second conductive element, and a concentration of the second material varies in concentration from a relatively higher amount at a location disposed toward the second conductive element to a relatively lower amount toward the first conductive element.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: June 4, 2024
    Assignee: Adeia Semiconductor Technologies LLC
    Inventor: Cyprian Emeka Uzoh
  • Patent number: 11979977
    Abstract: A method for manufacturing a circuit board including: providing at least one wiring base board, the wiring base board comprising a first conductor layer, an insulation layer, and an alloy layer which are stacked in order, wherein a solder paste layer is formed on a side of the alloy layer, a part of the alloy layer is exposed out of the solder paste layer to form a thermal conductive surface; providing a core layer; and pressing two wiring base boards on two opposite sides of the core layer to form a sealed heat dissipating chamber between the thermal conductive surfaces of the two wiring base boards. The present disclosure further provides a circuit board having a heat dissipation structure.
    Type: Grant
    Filed: August 31, 2019
    Date of Patent: May 7, 2024
    Assignees: QING DING PRECISION ELECTRONICS (HUAIAN) CO., LTD, Avary Holding (Shenzhen) Co., Limited.
    Inventors: Hsiao-Ting Hsu, Tao-Ming Liao, Ming-Jaan Ho, Xian-Qin Hu, Fu-Yun Shen
  • Patent number: 11963301
    Abstract: A printed circuit board includes: an insulating layer; a first circuit layer disposed on one surface of the insulating layer, and including a first circuit pattern and a first connection pad; and a surface treatment layer disposed on one surface of the first connection pad. The other surface of the first connection pad is covered by the insulating layer, and at least a portion of a side surface of the first connection pad is spaced apart from the insulating layer.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: April 16, 2024
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Seong Ho Choi, Tae Seok Kim
  • Patent number: 11963298
    Abstract: A printed wiring board includes a base insulating layer, a conductor layer formed on the base layer and including first and second pads, a solder resist layer formed on the base layer, covering the conductor layer and having first opening exposing the first pad and second opening exposing the second pad, a first bump formed on the first pad and including a base plating layer and a top plating layer, and a second bump formed on the second conductor pad and including a base plating layer and a top plating layer. The second opening has diameter smaller than diameter of the first opening, the second bump has diameter smaller than diameter of the first bump, the first pad has a first recess formed on the first pad, the second pad has a second recess formed on the second pad, and the first recess is larger than the second recess.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: April 16, 2024
    Assignee: IBIDEN CO., LTD.
    Inventors: Yoshiki Matsui, Atsushi Deguchi
  • Patent number: 11956895
    Abstract: The disclosure relates to a printed circuit board having at least two current-conducting layer plies, wherein the current-conducting layer plies extend in an axial direction of the printed circuit board and are arranged in succession in a thickness direction of the printed circuit board. A component fastened by THT is arranged on one side of the printed circuit board. At least one connecting element extends through the printed circuit board through a passage opening in the thickness direction. The current-conducting layer ply is adjacent to the component fastened by THT reaches as far as the connecting element and the current-conducting layer ply that is remote from the component fastened by THT is at a distance from the connecting element.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: April 9, 2024
    Assignee: ZF Friedrichshafen AG
    Inventor: Michael Sperber
  • Patent number: 11956896
    Abstract: A printed wiring board includes a first insulating layer, a conductor layer, and a second insulating layer. The conductor layer includes first and second circuits such that space is formed between the circuits, the first circuit has first and second side walls, the second circuit has third and fourth side walls such that the second wall faces the third wall, the first circuit has first, second and third portions, the second circuit has fourth, fifth and sixth portions such that the first and fourth portions, the second and fifth portions and the third and sixth portions face each other, the first circuit is formed such that the second wall of the second portion is recessed from the second wall of the first and third portions, and the first insulating layer has recess between the second and fifth portions such that the second insulating layer is filling the space and recess.
    Type: Grant
    Filed: February 21, 2022
    Date of Patent: April 9, 2024
    Assignee: IBIDEN CO., LTD.
    Inventors: Tomohiko Murata, Yoshiteru Hashimoto, Yoshiki Kawai, Hideyuki Goto
  • Patent number: 11943867
    Abstract: An electronic component includes a main body portion that has a first main surface having first and second sides, a second main surface opposite to the first main surface, a first side surface sharing the first side with the first main surface, and a second side surface sharing the second side with the first main surface, connection terminals that have electrical conductivity and that are arranged on the first main surface so as to be isolated from each other, and side-surface terminals that have electrical conductivity. The main body portion has side-surface grooves that are formed in the first and second side surfaces and that extend from the first main surface toward the second main surface. The side-surface terminals are provided on inner sides of the side-surface grooves and are each electrically connected to at least one of two end portions of the corresponding connection terminal.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: March 26, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Naofumi Takezono
  • Patent number: 11937373
    Abstract: One aspect of the instant application provides techniques to reduce the amount of crosstalk on single-ended signals in the pin field region of an integrated circuit device on a printed circuit board (PCB). The PCB can include a plurality of layers and an array of vias comprising a plurality of rows configured to route signals across layers. An inner layer of the PCB can include first and second signal traces positioned between first and second adjacent rows of the vias, the first signal trace positioned adjacent to the first row and the second signal trace positioned adjacent to the second row. The first signal trace can include at least one curved segment that curves around a substantial portion of a corresponding via in the first row such that separation between the first and second signal traces varies along the curved segment.
    Type: Grant
    Filed: March 8, 2022
    Date of Patent: March 19, 2024
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Melvin K. Benedict, Paul Danna, Chi Kim Sides, Wayne Vuong, Michael Chan
  • Patent number: 11930589
    Abstract: A printed wiring board includes a lower layer including conductor layers and insulating layers, a conductor layer formed on the outermost insulating layer in the lower layer, and a solder resist layer formed on the conductor layer such that the solder resist layer is covering the conductor layer on the outermost insulating layer, and a two-dimensional code structure formed on the lower layer and including the conductor layer and a portion of the solder resist layer such that the portion of the solder resist layer has openings forming exposed portions of the conductor layer and that the openings of the solder resist layer and the exposed portions of the conductor layer form the two-dimensional code structure. The conductor layer includes a portion corresponding to the two-dimensional code structure such that the portion of the conductor layer has a residual copper rate that allows the two-dimensional code structure to be read.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: March 12, 2024
    Assignee: IBIDEN CO., LTD.
    Inventor: Yoshihiko Hayashi
  • Patent number: 11917757
    Abstract: A circuit board includes a substrate including first and second sections with different thicknesses, a protective layer, and mounting electrodes. The substrate includes a step surface connecting a first principal surface of the first section and a first principal surface of the second section. The mounting electrodes are on the first principal surface corresponding to an element to be mounted. The protective layer is disposed over the first principal surface, the step surface, and the first principal surface. The separation distance between the mounting electrode and the step surface is greater than or equal to the terminal-to-terminal distance between the mounting electrode and the mounting electrode.
    Type: Grant
    Filed: October 7, 2021
    Date of Patent: February 27, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Hiroki Maegawa