Patents Examined by Ishwarbhai B. Patel
  • Patent number: 11570882
    Abstract: A substrate for mounting electronic element includes: a first substrate including a first surface and a second surface opposite to the first surface; a second substrate including a third surface and a fourth surface opposite to the third surface; and heat dissipation bodies each including a fifth surface and a sixth surface opposite to the fifth surface. The first substrate includes at least one mounting portion for at least one electronic element at the first surface. Heat conduction of the heat dissipation bodies in a direction perpendicular to a longitudinal direction of the at least one mounting portion and perpendicular to a direction along opposite sides of the second substrate is greater than heat conduction of the heat dissipation bodies in the longitudinal direction of the at least one mounting portion and in the direction along opposite sides of the second substrate in a transparent plan view of the substrate.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: January 31, 2023
    Assignee: KYOCERA CORPORATION
    Inventors: Yukio Morita, Noboru Kitazumi, Yousuke Moriyama
  • Patent number: 11558961
    Abstract: A printed circuit board includes a first insulating layer having a through hole, and a via disposed to fill the through hole and to be extended to at least one surface of the first insulating layer, wherein the via includes a plating layer having an inner wall part disposed on an inner wall of the through hole and a land part extended from the inner wall part and disposed on the at least one surface of the first insulating layer, and a metal paste layer including metal particles, and filled in the rest of the through hole and disposed on the plating layer.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: January 17, 2023
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jungwoo Choi, Tae-hong Min
  • Patent number: 11553586
    Abstract: A wiring substrate which includes a base member having a first surface, a first differential signal line disposed on the first surface of the base member and a second differential signal line disposed adjacent to the first differential signal line on the first surface of the base member. A ground layer which faces the first and second differential signal lines, has a plurality of openings continuously arranged along a predetermined direction. In a planar view of the wiring substrate, where a length of each of the plurality of openings in a direction along the signal lines is a length L1, a length of the opening in a direction orthogonal to Li is a length L2, and a distance between the first and second differential signal lines is a length L3, L1 is equal to or greater than four times L2, and L2 is equal to or less than L3.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: January 10, 2023
    Assignee: Canon Kabushiki Kaisha
    Inventors: Toshiyuki Yoshida, Yu Ogawa, Shoji Matsumoto
  • Patent number: 11553592
    Abstract: A ceramic substrate of the present disclosure is a ceramic substrate including a ceramic body having a ceramic layer on a surface thereof and a surface electrode placed on a primary face of the ceramic body. Between the surface electrode and the ceramic layer is an oxide layer made of an insulating oxide having a melting point higher than the firing temperature for the ceramic layer. The oxide layer also extends on the ceramic layer not occupied by the surface electrode. The oxide layer on the ceramic layer not occupied by the surface electrode has a rough surface.
    Type: Grant
    Filed: May 4, 2021
    Date of Patent: January 10, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Ryota Asai, Yosuke Matsushita
  • Patent number: 11552009
    Abstract: A printed circuit board includes: a first insulating layer; a first wiring layer disposed on one surface of the first insulating layer; and a bump at least partially disposed in the first insulating layer and connected to the first wiring layer. The bump at least partially protrudes from the other surface of the first insulating layer, opposite to the one surface of the first insulating layer.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: January 10, 2023
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventor: Seong Ho Choi
  • Patent number: 11546985
    Abstract: The present application discloses a differential signal routing line of a circuit board and a circuit board, which comprises a circuit board, and the circuit board is provided with differential signal routing lines including a first differential signal routing line and a second differential signal routing line that are disposed at different layers of the circuit board.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: January 3, 2023
    Assignee: HKC CORPORATION LIMITED
    Inventor: Shuixiu Hu
  • Patent number: 11528804
    Abstract: A printed circuit board includes: an insulating layer; and a first circuit layer disposed on an upper surface of the insulating layer. A lower surface of the first circuit layer is in contact with at least a portion of the insulating layer, and the first circuit layer includes a first region embedded in the insulating layer, and a second region protruding from the upper surface of the insulating layer.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: December 13, 2022
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Ga Young Yoo, Mi Sun Hwang, Jun Hyeong Jang
  • Patent number: 11528803
    Abstract: A wiring circuit board assembly sheet includes a support sheet having two end edges parallel with each other and a plurality of wiring circuit boards disposed at spaced intervals to each other in the support sheet. The wiring circuit board includes a metal-based portion having a generally rectangular frame shape. The metal-based portion includes a first piece along a first direction perpendicular to a thickness direction of the support sheet, and a second piece along a second direction perpendicular to the thickness direction and the first direction. Both the first piece and the second piece are inclined with respect to the end edge of the support sheet.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: December 13, 2022
    Assignee: NITTO DENKO CORPORATION
    Inventors: Takuya Taniuchi, Naoki Shibata, Ryosuke Sasaoka, Yasunari Oyabu
  • Patent number: 11523501
    Abstract: A stretchable electronic device includes a substrate, a plurality of electronic elements, and a conductive wiring. The electronic elements and the conductive wiring are disposed on the substrate, and the conductive wiring is electrically connected to the electronic elements. The conductive wiring is formed by stacking an elastic conductive layer and a non-elastic conductive layer. A fracture strain of the elastic conductive layer is greater than a fracture strain of the non-elastic conductive layer, and the non-elastic conductive layer includes a plurality of first fragments which are separated from one another.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: December 6, 2022
    Assignee: Au Optronics Corporation
    Inventors: Tsung-Ying Ke, Chun-Nan Chen, Zih-Shuo Huang
  • Patent number: 11523511
    Abstract: A first microchip includes holes or sockets along or in a top face or surface of the first microchip and a second microchip includes nodules extending from a edge of the second microchip. The nodules of the second microchip are received in the holes or sockets along or in the top face or surface of the first microchip, whereupon the first and second microchips are positioned transverse or perpendicular to each other.
    Type: Grant
    Filed: February 3, 2021
    Date of Patent: December 6, 2022
    Assignee: Indiana Integrated Circuits, LLC
    Inventors: Jason M. Kulick, Tian Lu
  • Patent number: 11516906
    Abstract: The circuit board according to the present invention includes a wiring portion and a non-wiring portion, the wiring portion having a metal layer and a resin layer, the non-wiring portion having a resin layer, the resin layer at a frequency 10 GHZ having a relative permittivity of from 2 to 3 at 23° C., and the circuit hoard satisfying a relationship: (A?B)/B?0.1 wherein A is the maximum value of the thickness in the wiring portion (?m) and B is the minimum value of the thickness in the non-wiring portion (?m).
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: November 29, 2022
    Assignee: JSR CORPORATION
    Inventors: Isao Nishimura, Nobuyuki Miyaki, Toshiaki Kadota, Shintarou Fujitomi, Tomotaka Shinoda
  • Patent number: 11516914
    Abstract: A printed circuit board includes: a base substrate including a unit region; a plurality of connection pads disposed on one surface of the base substrate; and first and second lead-in lines disposed on the one surface and respectively connected to at least a portion of the plurality of connection pads. The first and second lead-in lines have first and second cut surfaces on the one surface, respectively. The first cut surface is disposed in a position spaced apart from a side surface of the printed circuit board. The second cut surface is exposed to the side surface of the printed circuit board.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: November 29, 2022
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventor: Seong Ho Choi
  • Patent number: 11497115
    Abstract: Carrier board structure with an increased core-layer trace area and method for manufacturing the same are introduced. The carrier board structure comprises a core layer structure, a first circuit build-up structure, and a second circuit build-up structure. The core layer structure comprises a core layer, a signal transmission portion, and an embedded circuit layer, wherein the signal transmission portion and the embedded circuit layer are disposed inside the core layer and electrically connected. The first circuit build-up structure is disposed on the core layer on a same side as the embedded circuit layer and is electrically connected to the embedded circuit layer. The second circuit build-up structure is disposed on the core layer on a same side as the signal transmission portion, and is electrically connected to the first circuit build-up structure through the signal transmission portion and the embedded circuit layer.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: November 8, 2022
    Assignee: Unimicron Technology Corp.
    Inventors: Yi Lin, Hsiao-Han Huang, Yu-Hsin Pan
  • Patent number: 11497116
    Abstract: A flexible circuit board is provided. The flexible circuit board includes a base film with an outer lead region defined on either one surface or the other surface and an outer lead provided in the outer lead region and connected to an electronic device, in which the outer lead includes a plurality of first outer leads and a plurality of second outer leads formed to be spaced apart from each other so as to face each other in the outer lead region, and in which the number of the plurality of first outer leads is greater than the number of the plurality of second outer leads.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: November 8, 2022
    Assignee: STEMCO CO., LTD.
    Inventors: Jin Han Lee, Sung Bin Park, Hiroo Shimizu, Dong Eun Son
  • Patent number: 11490513
    Abstract: According to one embodiment, a metal base circuit board includes a metal base substrate, a first circuit pattern, and a first insulating layer between the metal base substrate and the first circuit pattern. The first insulating layer covers a lower surface of the first circuit pattern and at least part of a side surface of the first circuit pattern, the lower surface facing the metal base substrate, the at least part of the side surface being adjacent to the lower surface.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: November 1, 2022
    Assignee: NHK SPRING CO., LTD.
    Inventors: Katsumi Mizuno, Daiki Ikeda
  • Patent number: 11483923
    Abstract: A component carrier for carrying at least one electronic component includes (a) a plurality of electrically conductive layers; (b) a plurality of electrically insulating layers; and (c) a thermoplastic structure. The electrically conductive layers, the electrically insulating layers, and the thermoplastic structure form a laminate. Further, a method for manufacturing such a component carrier and an electronic apparatus including such a component carrier are provided.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: October 25, 2022
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventor: Thomas Krivec
  • Patent number: 11452199
    Abstract: An electronic device including a first component carrier, a second component carrier connected with the first component carrier so that a thermal decoupling gap is formed between the first component carrier and the second component carrier, a first component on and/or in the second component carrier, and a second component having a first main surface mounted in the thermal decoupling gap so that at least part of an opposing second main surface and an entire sidewall of the second component is exposed with respect to material of the first component carrier and with respect to material of the second component carrier.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: September 20, 2022
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventors: Martin Schrems, Markus Leitgeb, Steve Anderson
  • Patent number: 11452210
    Abstract: An embodiment is a wiring substrate that includes a first metal plate. The first metal plate includes a first electrode and a wiring, and the wiring includes a mount portion for an electronic component. The wiring substrate further includes a second metal plate. The second metal plate includes a second electrode diffusion-bonded to an upper surface of the first electrode. The second metal plate includes a first opening that exposes the mount portion. The first opening is large enough to accommodate the electronic component.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: September 20, 2022
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Takayuki Matsumoto, Tsukasa Nakanishi, Yukinori Hatori
  • Patent number: 11445599
    Abstract: A multi-layer PCB has conductive vias (134) passing through multiple layers. A layer may have a conductive non-functional feature (710) physically contacting a via but not surrounding the via, to make the PCB more resistant to thermal stresses while, at the same time, reducing the parasitic capacitance compared to a prior art non-functional pad (310n).
    Type: Grant
    Filed: August 20, 2020
    Date of Patent: September 13, 2022
    Assignee: Dell Products L.P.
    Inventors: Umesh Chandra, Bhyrav M. Mutnury
  • Patent number: 11445617
    Abstract: A package structure is disclosed herein. The package structure includes an insulating composite layer, a sealant disposed on the insulating composite layer, a first chip embedded in the sealant and having a plurality of first conductive pads exposed through the sealant, a circuit layer module having a plurality of circuit layers and a plurality of dielectric layers having a plurality of conductive vias, a second chip embedded in the circuit layer module and has a plurality of second conductive pads electrically connected to the circuit layers through the conductive vias, and a protecting layer having a plurality of openings disposed on the circuit layer module, in which the openings expose a portion of the circuit layer module.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: September 13, 2022
    Assignee: Unimicron Technology Corp.
    Inventors: Kai-Ming Yang, Chen-Hao Lin, Cheng-Ta Ko, John Hon-Shing Lau, Yu-Hua Chen, Tzyy-Jang Tseng