Patents Examined by Ishwarbhai B. Patel
  • Patent number: 10440836
    Abstract: Provided is a double layer circuit board and a manufacturing method thereof. The double layer circuit board comprises a substrate, a first circuit layer formed on a first surface of the substrate, a second circuit layer formed on a second surface of the substrate, and at least one connecting pillar formed in and covered by the substrate. Each one of the at least one connecting pillar includes a first end connected to the first circuit layer and a second end connected to the second circuit layer. A terminal area of the second end is greater than a terminal area of the first end. Therefore, the second circuit layer is firmly connected to the first circuit layer through the at least one connecting pillar. A yield rate of the double layer circuit board may be increased.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: October 8, 2019
    Assignee: KINSUS INTERCONNECT TECHNOLOGY CORP.
    Inventors: Ting-Hao Lin, Chiao-Cheng Chang, Yi-Nong Lin
  • Patent number: 10440818
    Abstract: This present invention provides a flexible circuit board substrate including: a conductive material layer with a first surface, a second surface opposite to the first surface, and at least one via hole throughout the first surface and the second surface; a first surface-treated layer with a plurality of first particles and a plurality of second particles formed on the first surface and/or the second surface, wherein each first particle has a diameter greater than that of each second particle; and an insulating structure formed on the first surface-treated layer and filled up with the via hole, and a method of manufacturing the same.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: October 8, 2019
    Assignee: Shirre Lab Corp.
    Inventor: Shih-Ing Chan
  • Patent number: 10431381
    Abstract: A multilayer capacitor includes: a capacitor body having a length and a width substantially equal to each other, including dielectric layers and a plurality of first and second internal electrodes, and having first to sixth surfaces; and first and second external electrodes disposed on third and fourth surfaces of the capacitor body and extending to cover a portion of fifth and sixth surfaces of the capacitor body, respectively; wherein the first internal electrode has a first lead portion exposed to a first corner of the capacitor body in which the third and fifth surfaces of the capacitor body meet each other and covered with the first external electrode, and the second internal electrode has a second lead portion exposed to a second corner of the capacitor body at which the fourth and sixth surfaces of the capacitor body meet each other and covered with the second external electrode.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: October 1, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventor: Dong Su Cho
  • Patent number: 10433426
    Abstract: A circuit board includes a substrate, a first dielectric layer, an adhesive layer, a second dielectric layer, and a first conductive line. The first dielectric layer is disposed on the substrate. The adhesive layer is bonded to the first dielectric layer and has a top surface opposite to the substrate. The second dielectric layer is disposed on the adhesive layer and has at least one first through hole. The first conductive line is located in the first through hole of the second dielectric layer and is in contact with the top surface of the adhesive layer.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: October 1, 2019
    Assignee: UNIMICRON TECHNOLOGY CORP.
    Inventor: Po-Hsuan Liao
  • Patent number: 10424547
    Abstract: A substrate for packaging a semiconductor device is disclosed. The substrate includes a first dielectric layer having a first surface and a second surface opposite to the first surface, a first patterned conductive layer adjacent to the first surface of the first dielectric layer, and a second patterned conductive layer adjacent to the second surface of the first dielectric layer. The first dielectric layer includes a first portion adjacent to the first surface, a second portion adjacent to the second surface, and a reinforcement structure between the first portion and the second portion. A thickness of the first portion of the first dielectric layer is different from a thickness of the second portion of the first dielectric layer.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: September 24, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING INC.
    Inventors: Chih Cheng Lee, Yuan-Chang Su
  • Patent number: 10426031
    Abstract: A method for producing a flexible printed circuit board according to an embodiment of the present invention includes a through-hole formation step of preparing a base material including a base film having insulating properties and flexibility and a pair of metal films stacked on both surface sides of the base film, and forming a through-hole in the metal film on a front surface side of the base material and the base film; a filling step of stacking, by electroplating on a front surface of the base material, stacking a conductive material on a surface of the metal film on the front surface side to form a conductive material layer and to fill the through-hole with the conductive material; and a removal step of removing, by etching the front surface of the base material, a surface layer of the conductive material layer stacked on the surface of the metal film on the front surface side and a surface layer of the conductive material filling the through-hole.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: September 24, 2019
    Assignee: SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.
    Inventors: Tadahiro Kaibuki, Kozo Sato
  • Patent number: 10420213
    Abstract: Printed circuit boards having an increased density of vertical interconnect paths, as well as methods for their manufacture. One example may provide a printed circuit board having an increased density of vertical interconnect paths by forming a plurality of segmented vias. The segmented vias may extend through interior layers of the printed circuit board. The segmented vias may be formed of portions of vias in the interior layers of the printed circuit board. An area between three or more segmented vias may be filled with resin or other material or materials.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: September 17, 2019
    Assignee: Apple Inc.
    Inventors: Mark J. Beesley, Albert A. Onderick, II, Anne M. Mason, Craig A. Gammel, Shawn X. Arnold
  • Patent number: 10405421
    Abstract: A layup for multiple-layer printed circuit board manufacturing is formed according to a process that includes selectively applying a dielectric resin to a high resin demand region of a circuitized core layer without applying the dielectric resin to another region of the circuitized core layer. The process also includes partially curing the dielectric resin within the high resin demand region. The process further includes forming a layup that includes a layer of pre-impregnated (prepreg) material adjacent to the partially cured dielectric resin within the high resin demand region of the circuitized core layer.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: September 3, 2019
    Assignee: International Business Machines Corporation
    Inventors: Bruce J. Chamberlin, Matthew S. Kelly, Scott B. King, Joseph Kuczynski
  • Patent number: 10398030
    Abstract: A multilayer electronic component includes a multilayer capacitor including a capacitor body in which internal electrodes are stacked to be parallel with respect to a mounting surface and external electrodes disposed on opposing end surfaces of the capacitor body, respectively, and a metal frame having a solder pocket and including a vertical portion, an upper horizontal portion extending from an upper end of the vertical portion, and a lower horizontal portion extending from a lower end of the vertical portion, the upper horizontal portion connected to an upper band portion of each of the external electrodes. 0.1?G/CT?0.7 is satisfied, in which CT is a height of the vertical portion and G is a distance between the lower band portion of each of the external electrodes and a lower end of the metal frame.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: August 27, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Heung Kil Park, Gu Won Ji, Se Hun Park
  • Patent number: 10383234
    Abstract: A molding with an integrated electrode pattern, including a resin molded body having a first surface and a second surface opposing each other; a first film that is formed on the first surface and that includes an electrode pattern and a first lead-out wire electrically connected to the electrode pattern, the first film not being covered by the resin molded body; and a second film that stands on the first surface, and that includes a second lead-out wire electrically connected to the first lead-out wire, the second film having a rectangular shape, and the resin molded body includes a pair of support wall portions formed integrally with the first surface so as to stand on the first surface and clamp both ends of a base part of the second film.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: August 13, 2019
    Assignee: NISSHA CO., LTD.
    Inventors: Seiichi Yamazaki, Toshihiro Iga, Yasuisa Takinishi
  • Patent number: 10368438
    Abstract: A printed wiring board includes a laminated base material including an insulating layer and a conductor layer formed on the insulating layer, and a solder resist layer laminated on the laminated material and including photosensitive resin. The resist layer has surface portion and portion in contact with the laminated material, the conductor layer has pattern including conductor pads in contact with the resist layer such that the pads are positioned in openings in the resist layer, and the resist layer satisfies a first condition that a chemical species derived from a photopolymerization initiator has concentration higher in the portion in contact with the laminated material than concentration in the surface portion and/or a second condition that the chemical species derived from the initiator in the portion in contact with the laminated material has photopolymerization initiating ability higher than a chemical species derived from a photopolymerization initiator in the surface portion.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: July 30, 2019
    Assignee: IBIDEN CO., LTD.
    Inventors: Hiroyuki Nishioka, Shinsuke Ishikawa
  • Patent number: 10368435
    Abstract: The present invention relates generally to electric circuit testing, building, or implementing using a breadboard style PCB. Aspects of the present invention include eliminating the need to use hookup wires when building and testing electric circuits on PCBs. In embodiments, a PCB system having rows and columns of signal tie points connected in a breadboard layout and using an embedded wire and a solder bridge to form partial connections between signal tie points. In embodiments, the embedded wire and solder bridge is capable of connecting a column of signal tie points. In embodiments, the embedded wire and solder bridge is capable of connecting a power rail to a signal tie point. Thus, a circuit can be implemented and tested by applying a small amount of solder to the solder bridge without the need for hookup wires.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: July 30, 2019
    Inventor: Samuel P. Kho
  • Patent number: 10362667
    Abstract: A circuit board is disclosed. In addition to insulating layers, the circuit board includes a structure for heat transfer that includes a first layer that is formed of graphite or graphene, a second layer that is formed of metallic material and disposed on one surface of the first layer, and a third layer that is formed of metallic material and disposed on the other surface of the first layer, and at least a portion of the structure for heat transfer is inserted into an insulation layer. Such a circuit board provides improved heat management. Also disclosed is a method of manufacturing the circuit board.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: July 23, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Tae-Hong Min, Myung-Sam Kang, Jung-Han Lee, Young-Gwan Ko
  • Patent number: 10356896
    Abstract: A self-healing wire includes, an electric wire arranged on a substrate, and a hybrid structure in which the electric wire is covered with at least one fluid selected from the group consisting of a fluid having conductive particles dispersed therein and a fluid having metal ions dissolved therein, formed on a healing portion for a crack to be generated in the electric wire. And a stretchable device includes the self-healing wire formed on a stretchable base material and an electric element mounted only on a base material higher in rigidity than the stretchable base material. Even when a crack is generated in the electric wire due to stretching of the substrate having flexibility, the crack is bridged by the conductive particles or a solid metal deposited from the metal ions in the fluid. Thus the self-healing wire and the stretchable device having both high conductivity and high stretchability are provided.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: July 16, 2019
    Assignee: WASEDA UNIVERSITY
    Inventors: Eiji Iwase, Tomoya Koshi
  • Patent number: 10342126
    Abstract: A method of making an electronic device includes forming a circuit layer on a liquid crystal polymer (LCP) substrate and having at least one solder pad. The method also includes forming an LCP solder mask having at least one aperture therein alignable with the at least one solder pad. The method further includes aligning and laminating the LCP solder mask and the LCP substrate together, then positioning solder paste in the at least one aperture. At least one circuit component may then be attached to the at least one solder pad using the solder paste.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: July 2, 2019
    Assignee: HARRIS CORPORATION
    Inventors: Louis Joseph Rendek, Jr., Travis L. Kerby, Casey Philip Rodriguez
  • Patent number: 10327327
    Abstract: In a suspension board, a first insulating layer is formed on a support substrate. A ground layer and a power wiring trace are formed on the first insulating layer. The ground layer has electric conductivity higher than that of the support substrate. A second insulating layer is formed on the first insulating layer to cover the ground layer and the power wiring trace. A write wiring trace is formed on the second insulating layer to overlap with the ground layer. In a stacking direction of the support substrate, the first insulating layer and the second insulating layer, a distance between the ground layer and the write wiring trace is larger than a distance between the power wiring trace and the write wiring trace.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: June 18, 2019
    Assignee: NITTO DENKO CORPORATION
    Inventors: Daisuke Yamauchi, Hiroyuki Tanabe
  • Patent number: 10319525
    Abstract: A multi-layer ceramic capacitor assembly includes a multi-layer ceramic capacitor comprising a laminate, the laminate having dielectric layers and internal electrodes laminated alternately therein, and external electrodes being electrically connected with the internal electrodes and disposed at end portions of the laminate; and an electrode-forming substrate coupled to the multi-layer ceramic capacitor and having through-holes disposed to correspond to the external electrodes.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: June 11, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Soon-Ju Lee, Young-Ghyu Ahn, Kyoung-Jin Jun, Sang-Soo Park, So-Yeon Song, Heung-Kil Park
  • Patent number: 10321565
    Abstract: A printed circuit board assembly includes a printed circuit board, at least one electronic device, a holder and a heat-dissipation device. The printed circuit board includes at least one first through hole. The electronic device includes a first surface, a second surface and at least one pin. The first surface and the second surface are opposite to each other, and the pin passes through the first through hole of the printed circuit board and is inserted on the printed circuit board. The holder is disposed between the printed circuit board and the electronic device. The holder includes a supporting surface sustaining the first surface of the electronic device. The heat-dissipation device includes a heat-dissipation surface attached to the second surface of the electronic device.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: June 11, 2019
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Ching-Chi Kuo, Yi-Hwa Hsieh
  • Patent number: 10321560
    Abstract: A printed circuit board (PCB) has multiple layers, where select portions of inner layer circuitry, referred to as inner core circuitry, are exposed from the remaining layers. The PCB having an exposed inner core circuitry is formed using a dummy core plus plating resist process. The select inner core circuitry is part of an inner core. The inner core corresponding to the exposed inner core circuitry forms a semi-flexible PCB portion. The semi-flexible PCB portion is an extension of the remaining adjacent multiple layer PCB. The remaining portion of the multiple layer PCB is rigid. The inner core is common to both the semi-flexible PCB portion and the remaining rigid PCB portion.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: June 11, 2019
    Assignee: Multek Technologies Limited
    Inventors: Pui Yin Yu, Mark Zhang, Jiawen Chen
  • Patent number: 10319664
    Abstract: A bonded body is provided in which an aluminum alloy member formed from an aluminum alloy, and a metal member formed from copper, nickel, or silver are bonded to each other. The aluminum alloy member is constituted by an aluminum alloy in which a concentration of Si is in a range of 1 mass % to 25 mass %. The aluminum alloy member and the metal member are subjected to solid-phase diffusion bonding. A compound layer, which is formed through diffusion of Al of the aluminum alloy member and a metal element of the metal member, is provided at a bonding interface between the aluminum alloy member and the metal member. A Mg-concentrated layer, in which a concentration of Mg is to 3 mass % or greater, is formed at the inside of the compound layer, and the thickness of the Mg-concentrated layer is in a range of 1 ?m to 30 ?m.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: June 11, 2019
    Assignee: MITSUBISHI MATERIALS CORPORATION
    Inventors: Nobuyuki Terasaki, Yoshiyuki Nagatomo