Patents Examined by Ishwarbhai B. Patel
  • Patent number: 10856421
    Abstract: A circuit board is disposed on a substrate and includes a dielectric layer and a circuit layer. The dielectric layer is disposed on the substrate. The circuit layer is embedded in the dielectric layer and has plural traces. Each of the traces has a first top surface and a first bottom surface which are opposite to each other, and the first bottom surface faces toward the substrate. The first top surface is exposed from the dielectric layer, and an area of a vertical projection of the first top surface on the substrate is smaller than an area of a vertical projection of the first bottom surface on the substrate.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: December 1, 2020
    Assignee: UNIMICRON TECHNOLOGY CORP.
    Inventors: Ching-Hao Huang, Ho-Shing Lee, Yu-Cheng Lin
  • Patent number: 10847317
    Abstract: An electronic component that includes a substrate having a first main surface and a second main surface, an element on the first main surface of the substrate, a first contact electrode electrically connected to the element, an insulating film defining a first opening at a position that has an overlap with the first contact electrode in the plan view of the first main surface, a protective film covering the insulating film in a region including at least a part of the periphery of the first opening, and a first external electrode electrically connected to the first contact electrode and extending over the protective film.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: November 24, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yasunobu Hayashi, Nobuhiro Ishida
  • Patent number: 10842017
    Abstract: A multi-layer PCB has conductive vias (134) passing through multiple layers. A layer may have a conductive non-functional feature (710) physically contacting a via but not surrounding the via, to make the PCB more resistant to thermal stresses while, at the same time, reducing the parasitic capacitance compared to a prior art non-functional pad (310n).
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: November 17, 2020
    Assignee: DELL PRODUCTS L.P.
    Inventors: Umesh Chandra, Bhyrav M. Mutnury
  • Patent number: 10833002
    Abstract: Provided is a connection structure for a semiconductor package which includes: a first passivation layer having an opening; a first conductive pattern that penetrates the first passivation layer and protrudes upwardly from the first passivation layer; a second passivation layer on the first passivation layer and covering the first conductive pattern; a second conductive pattern on the second passivation layer and electrically connected to the first conductive pattern; a third passivation layer on the second passivation layer and covering the second conductive pattern; and an external terminal in the opening and electrically connected to the first conductive pattern, wherein the first conductive pattern is thicker than the second conductive pattern.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: November 10, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jongyoun Kim
  • Patent number: 10808329
    Abstract: The wired circuit board includes a metal supporting board, an insulating layer and a conductor layer disposed at one side in the thickness direction of the metal supporting board, a gold plate layer disposed at the other side in the thickness direction of the metal supporting board, and an adherence layer disposed between the metal supporting board and the gold plate layer. The material of the metal supporting board is a corrosion resistant alloy. In the adherence layer, gold and the metal contained in the corrosion resistant alloy are mixedly present.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: October 20, 2020
    Assignee: NITTO DENKO CORPORATION
    Inventors: Yuu Sugimoto, Hiroyuki Tanabe
  • Patent number: 10798819
    Abstract: Flexible fingers for flexible printed circuits improve the crack resistance of prior art designs. The crack resistance can be improved by encapsulating the trace inside additional layers such that the outer two layers include only the lands of the through-hole, and all other copper is etched away. The crack resistance can also be improved with strategically adding copper on layers other than the trace layer including attaching is to the land of the through-hole as a stub. These two designs can be combined to include a stub trace into a four-layered design.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: October 6, 2020
    Assignee: COMMSCOPE, INC. OF NORTH CAROLINA
    Inventors: Brian J. Fitzpatrick, Jeffrey Cook, Jitendra Hansalia, Amid Ihsan Hashim
  • Patent number: 10796818
    Abstract: The present specification relates to a heating element and a method for manufacturing the same.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: October 6, 2020
    Assignee: LG CHEM., LTD.
    Inventors: Ji Eun Myung, Sera Kim, Jooyeon Kim, Chang Yoon Lim, Seung Heon Lee, Mun Seop Song, Kwang Joo Lee, Ji Young Hwang
  • Patent number: 10796925
    Abstract: Disclosed herein is a ceramic circuit substrate for a power module obtained by applying an insulating resin for preventing solder flow and chip displacement and an insulating resin for preventing partial discharges and the lowering of insulation to a main surface of a metal circuit and to the outer periphery of the metal circuit or between metal circuits, respectively. Also disclosed herein are methods for manufacturing a ceramic circuit substrate for a power module.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: October 6, 2020
    Assignee: Denka Company Limited
    Inventors: Akimasa Yuasa, Kouji Nishimura
  • Patent number: 10785876
    Abstract: An intermediate printed board has a plurality of unit regions that are to be cut out and separated to become a plurality of individual printed circuit boards, respectively. The intermediate printed board includes a metal core substrate including: a metal layer; and a plating layer formed on each of a top surface and a bottom surface of the metal layer, the plating layer being absent in each of cutting regions, the cutting regions being regions on the intermediate printed board where the plurality of unit regions are separated so as to produce the plurality of individual printed circuit boards; an insulating layer formed so as to cover a surface of the metal core substrate; and a conductive pattern formed on the insulating layer.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: September 22, 2020
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Yuichi Sugiyama, Masashi Miyazaki
  • Patent number: 10779405
    Abstract: A landless multilayer circuit board includes a first substrate, a first circuit, at least one connecting pillar, a second substrate, and a second circuit. The second substrate is on the surface of the first substrate, covering the first circuit, and exposing at least one top of the at least one connecting pillar exposed out of a surface of the second substrate, wherein an area of a portion of the at least one connecting pillar that is exposed out of the surface of the second substrate is greater than an area of a portion of the at least one connecting pillar that is connected to the first circuit. The second circuit is on the surface of the second substrate and the at least one connecting pillar, and connected to the portion of the at least one connecting pillar that is exposed out of the surface of the second substrate.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: September 15, 2020
    Assignee: KINSUS INTERCONNECT TECHNOLOGY CORP.
    Inventors: Ting-Hao Lin, Chiao-Cheng Chang, Yi-Nong Lin
  • Patent number: 10779401
    Abstract: A flexible printed circuit board (FPC) is provided, which includes a dielectric layer. Copper foil layers and cover layers are sequentially provided from inside to outside on both sides of the dielectric layer. The cover layer on one side of the dielectric layer is provided with a reinforced plate. The FPC includes a bending area. The copper foil layer and the cover layer on one side at the bending area and the reinforced plate are each provided with a windowed area. Edges of the copper foil layer, the cover layer, and the reinforced plate that are defined by windowed areas are not in one vertical plane. In the structure, stress concentrations in the bending area are distributed, so that the tearing risk to the edges of the bending area is reduced, and the bending resistance of the flexible circuit board is enhanced.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: September 15, 2020
    Assignee: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.
    Inventor: Yan Chen
  • Patent number: 10772191
    Abstract: A printed circuit board includes a substrate having a top surface and a bottom surface. First non-ground nets and a ground net are disposed within a specific region on the top surface. A second non-ground net and a split ground net are disposed on the bottom surface. The second non-ground net is electrically connected to one of the first non-ground nets through a first via hole in the substrate. The second non-ground net is isolated from the split ground net by a gap. An outermost insulating layer on the bottom surface of the substrate covers the second non-ground net and the split ground net. A conductive layer is disposed on the outermost insulating layer corresponding to the specific region of the substrate in which the first non-ground nets and the ground net are arranged, such that the conductive layer overlaps with the first non-ground nets.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: September 8, 2020
    Assignee: MediaTek Inc.
    Inventor: Nan-Jang Chen
  • Patent number: 10772216
    Abstract: An electronic component includes a multilayer body including insulating base materials laminated on each other and including first and second main surfaces perpendicular or substantially perpendicular to a lamination direction, and an alignment mark is defined by a conductor on one of the insulating base materials. The multilayer body includes a first layer area at a side of the first main surface and a second layer area at a side of the second main surface with respect to the alignment mark. An insulating base material in the first layer area has higher translucency than an insulating base material in the second layer area. The alignment mark is a trapezoidal cross-sectional shape including a first base at the side of the first main surface and a second base at the side of second main surface, the first base being longer than the second base.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: September 8, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Shingo Ito
  • Patent number: 10763202
    Abstract: A multi-row wiring member configured of a plurality of wiring members arrayed in a matrix includes a resin layer, a first plating layer forming internal terminals, a plating layer forming wiring portions and a second plating layer forming external terminals. The first plating layer is formed in the resin layer with lower faces thereof uncovered in a bottom surface of the resin layer. The plating layer forming wiring portions is formed on the first plating layer in the resin layer. The second plating layer is formed in the resin layer on partial areas within areas of the plating layer forming wiring portions, with upper faces thereof being uncovered on a top-surface side of the resin layer. On a bottom-surface side of the resin layer, a metal frame is formed at a margin around an aggregate of individual wiring members arrayed in the matrix.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: September 1, 2020
    Assignee: OHKUCHI MATERIALS CO., LTD.
    Inventors: Kaoru Hishiki, Ichinori Iidani
  • Patent number: 10750619
    Abstract: Graphene oxide is used as an insulation barrier layer for metal deposition. After patterning and modification, the chemical characteristics of graphene oxide are induced. It can be used as the catalyst for electroless plating in the metallization process, so that the metal is only deposited on the patterned area. It provides the advantages of improving reliability and yield. The metallization structure includes a substrate, a graphene oxide catalytic layer, and a metal layer. It may be widely applied to the metallization of the fine pitch metal of a semiconductor package as well as the fine pitch wires of a printed circuit board (PCB), touch panels, displays, fine electrodes of solar cells, and so on.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: August 18, 2020
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventor: Ming-Huei Yen
  • Patent number: 10734297
    Abstract: An Ag underlayer-attached metallic member includes a metallic member joined with a body to be joined and an Ag underlayer formed on a joining surface of the metallic member with the body to be joined, the Ag underlayer includes a glass layer formed on a metallic member side and an Ag layer laminated on the glass layer, and an area proportion of voids in an Ag layer surface of the Ag underlayer is 25% or less.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: August 4, 2020
    Assignee: MITSUBISHI MATERIALS CORPORATION
    Inventors: Shuji Nishimoto, Yoshiyuki Nagatomo
  • Patent number: 10729007
    Abstract: A substrate structure with high reflectance includes a base material, a patterned circuit layer, an insulating layer and a metal reflecting layer. The base material includes a first surface and a second surface opposite to the first surface. The patterned circuit layer is disposed on the first surface. The insulating layer covers the patterned circuit layer and a part of the first surface exposed by the patterned circuit layer. The metal reflecting layer covers the insulating layer, and a reflectance of the metal reflecting layer is substantially greater than or equal to 85%. A manufacturing method of a substrate structure with high reflectance is also provided.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: July 28, 2020
    Assignee: UNIFLEX Technology Inc.
    Inventors: Cheng-I Tu, Ying-Hsing Chen, Meng-Huan Chia, Hsin-Ching Su, Yi-Chun Liu, Cheng-Chung Lai, Yuan-Chih Lee
  • Patent number: 10721824
    Abstract: Disclosed is a stretchable electronic device, including: a stretchable board having a surface for mounting one or more electric parts; and a stretchable conductive connecting body provided on the stretchable board, extended in a three-dimensional stereoscopic structure in the direction away from the surface, and having stretchability. The stretchable conductive connecting body comprises a conductive connecting part for attaching the upper surface of the stretchable conductive connecting body to the electric part so as to be electrically connected to an electrode of the electric part.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: July 21, 2020
    Inventor: Hyunmin Cho
  • Patent number: 10681809
    Abstract: Disclosed is a composite printed circuit board including a first printed circuit board (PCB) having a first circuit pattern mounted thereon, and a second PCB having a second circuit pattern mounted thereon, and the first PCB penetrates and is coupled to the second PCB so that the first circuit pattern is electrically connected to the second circuit pattern.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: June 9, 2020
    Assignee: LG ELECTRONICS INC.
    Inventor: Sunil Lee
  • Patent number: 10681820
    Abstract: A circuit board includes: a metal core base material including a first main surface, a second main surface on an opposite side of the first main surface, a side surface, and a projection that projects from the side surface; an outer cover including a first insulation layer that covers the first main surface, a second insulation layer that covers the second main surface, and a third insulation layer that covers the side surface; a first wiring layer provided in the first main surface with the first insulation layer interposed between the first wiring layer and the first main surface; a second wiring layer provided in the second main surface with the second insulation layer interposed between the second wiring layer and the second main surface; and a sealing portion that is made of an insulation material embedded in the outer cover and covers an end surface of the projection.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: June 9, 2020
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Tatsuro Sawatari, Norio Sekiguchi