Abstract: A flexible printed circuit board according to an embodiment includes: a substrate; and a circuit pattern disposed on the substrate, wherein the circuit pattern includes a plurality of first circuit patterns, a plurality of second circuit patterns, and a plurality of third circuit patterns, wherein the third circuit pattern includes a third-first pad portion, a third-second pad portion, and a third wiring portion connecting the third-first pad portion and the third-second pad portion, a plurality of fourth wiring portions are disposed between a plurality of third wiring portions, a line width of the third wiring portion is greater than a line width of the fourth wiring portion, and a distance between the third wiring portion and the fourth wiring portion adjacent to the third wiring portion is greater than a distance between the fourth wiring portions.

Abstract: A three-dimensional molded circuit component, includes: a base member which includes a metal part and a resin part; a circuit pattern which is formed on the resin part; and a mounted component which is mounted on the base member, and is electrically connected to the circuit pattern. The resin part includes a resin thin film as a portion thereof, which includes a thermoplastic resin, of which a thickness is in the range of 0.01 mm to 0.5 mm, and which is formed on the metal part. The mounted component is arranged on the metal part via the resin thin film.

Abstract: A circuit board includes a base layer, a seed layer formed on the base layer, and a first electrode layer formed on the seed layer. The seed layer is formed of a metal oxide with a thickness of 100 to 400 ?. The circuit board may further include an insulation layer formed on the first electrode layer and a second electrode layer formed on the insulation layer.

Abstract: A wiring substrate includes an insulating substrate, a conductor layer and an interlayer. The insulating substrate contains AlN. The conductor layer contains Cu. The interlayer is located between the insulating substrate and the conductor layer. In the interlayer, between a first region near the insulating substrate and a second region near the conductor layer, Cu concentration is higher in the second region than in the first region, and Al concentration is higher in the first region than in the second region.

Abstract: A semiconductor device includes: a substrate main body having a first surface and a second surface; an electric component arranged in the substrate main body; a surface conductor pattern arranged in a first circuit layer located on the second surface. Also included is a first internal conductor pattern and a second internal conductor pattern arranged in a second circuit layer located between the electric component and the second surface, and insulated from each other. Also, at least one first heat conductor via extends from the electric component to the first internal conductor pattern; and at least one second heat conductor via extends from the surface conductor pattern to the second internal conductor pattern.

Abstract: The present disclosure relates to a printed circuit board. The printed circuit board includes a core layer; a through portion penetrating through the core layer; a first via disposed to be spaced apart from an inner wall of the through portion within the through portion; and a second via disposed in the first via and having a diameter different from that of the first via.

Abstract: A package that includes a power amplifier and a substrate coupled to the power amplifier. The substrate includes an encapsulation layer, a capacitor device located in the encapsulation layer, an inductor located in the encapsulation layer, at least one first dielectric layer coupled to a first surface of the encapsulation layer, and a plurality of first interconnects coupled to the first surface of the encapsulation layer. The plurality of first interconnects is located at least in the at least one first dielectric layer. The plurality of first interconnects is coupled to the capacitor device and the inductor. The inductor and the capacitor device are configured to be electrically coupled together to operate as elements of a matching network for the power amplifier. The capacitor device is configured to be coupled to ground.

Abstract: A circuit board to be secured to a support member includes a first structure, a second structure, and a third structure. The first structure prevents the circuit board from moving in a horizontal direction with respect to the support member. The second structure prevents the circuit board from rotating around the first structure with respect to the support member. The third structure prevents the circuit board from moving in a vertical direction with respect to the support member. A distance between the first structure and the second structure is shorter than a distance between the first structure and the third structure.

Abstract: Provided is a connection structure for a semiconductor package which includes: a first passivation layer having an opening; a first conductive pattern that penetrates the first passivation layer and protrudes upwardly from the first passivation layer; a second passivation layer on the first passivation layer and covering the first conductive pattern; a second conductive pattern on the second passivation layer and electrically connected to the first conductive pattern; a third passivation layer on the second passivation layer and covering the second conductive pattern; and an external terminal in the opening and electrically connected to the first conductive pattern, wherein the first conductive pattern is thicker than the second conductive pattern.

Abstract: A conductive trace interconnect tape for use with a printed circuit board or a flexible circuit substrate comprises a top insulating layer, an electrically conductive layer, and a bottom insulating layer. The top insulating layer is formed from electrically insulating material and is configured to provide electrical isolation from electrically conductive objects that are positioned on top of the conductive trace interconnect tape. The electrically conductive layer is positioned underneath the top insulating layer. The electrically conductive layer is formed from electrically conductive material and includes electrical interconnect traces, electrical component pads, or electrically conductive planar portions. The bottom insulating layer is positioned underneath the electrically conductive layer.

Abstract: An electronic component includes: an insulating layer; and a first metal bump disposed on the insulating layer and provided with: a first metal layer disposed on the insulating layer; and a second metal layer disposed on the first metal layer, wherein, in a cross-sectional view of the electronic component, the first metal layer has a first width, the second metal layer has a second width, and the first width is smaller than the second width.

Abstract: Here are described composite panels comprising at least one integrated or embedded electrical circuit, their methods of manufacturing and their use in the aeronautic and aircraft industries. Also described are aircraft components including the composite panel as defined herein.

Abstract: A printed wiring board includes a first resin insulating layer, a second resin insulating layer formed on a surface of the first layer, and a conductor layer formed on the surface of the first layer such that the second layer is covering the conductor layer and that the conductor layer includes first, second, third, fourth, fifth, and sixth circuits such that the third and fourth circuits are sandwiching the first circuit and that the fifth and sixth circuits are sandwiching the second circuit. Widths between the first and third circuits and between the first and fourth circuits are 5 ?m to 14 ?m, and when a width between the second and fifth circuits and a width between the second and sixth circuits is 20 ?m or more, the upper surface of the first circuit, and the upper surface and side walls of the second circuit are formed to have unevenness.

Abstract: A component carrier includes a stack with at least one electrically conductive layer structure and at least one electrically insulating layer structure. At least one electrically insulating layer structure has at least partly tapering through holes filled substantially completely with an electrically conductive filling. The at least one electrically conductive layer structure and the electrically conductive filling are made of the same material. In addition, different ones of the through holes of one electrically insulating layer structure are tapering in opposite directions.

Abstract: A multilayer printed circuit board having a stackup including an upper half of the stackup and a lower half of the stackup, the multilayer printed circuit board having a top exposed surface and a bottom exposed surface, a first trace and via structure, having one portion disposed on the top exposed surface and another portion disposed within the upper half of the stackup, a second trace and via structure, having one portion disposed on the top exposed surface and another portion disposed within the upper half of the stackup, and first electrical components and second electrical components disposed on the top exposed surface of the multilayer printed circuit board and associated, respectively, with the first trace and via structure and the second trace and via structure, wherein the first electrical components are mounted orthogonally with respect to the second electrical components.

Abstract: Embodiments include a package substrate, a method of forming the package substrate, and a semiconductor package. A package substrate includes a conductive layer in a dielectric, a first trace and a first via pad of the conductive layer having a first thickness, and a second trace and a second via pad of the conductive layer having a second thickness. The second thickness of second trace and second via pad may be greater than the first thickness of the first trace and first via pad. The dielectric may include a first dielectric thickness and a second dielectric thickness, where the second dielectric thickness may be less than the first dielectric thickness. The package substrate may include a third via having a third thickness on the first via pad, and a fourth via having a fourth thickness on the second via pad, wherein the third thickness is greater than the fourth thickness.

Abstract: A printed circuit board includes an insulating layer and a circuit layer disposed on the insulating layer. The circuit layer includes a first circuit pattern and a second circuit pattern. Each of the first and second circuit patterns has a first side surface, a second side surface opposing the first side surface, and a top surface connected to ends of the first and second side surfaces, when viewed in a cross section direction. The first side surface of the first circuit pattern and the first side surface of the second circuit pattern face each other. A height of the first side surface of the first circuit pattern is greater than a height of the second side surface of the first circuit pattern, and a height of the first side surface of the second circuit pattern is greater than a height of the second side surface of the second circuit pattern.

Abstract: A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.

Abstract: A printed circuit board includes a first insulating layer, a second insulating layer disposed on a lower surface of the first insulating layer, an electronic component embedded in the second insulating layer and at least partially in contact with the first insulating layer, a first wiring layer disposed on an upper surface of the first insulating layer, a second wiring layer disposed on a lower surface of the second insulating layer, and a first wiring via penetrating through the first and second insulating layers and connecting at least portions of the first and second wiring layers to each other.

Abstract: A printed circuit board (PCB) includes: an insulation substrate; a first pad on the insulation substrate; and a second pad on the insulation substrate and spaced apart from the first pad, wherein the second pad has a size substantially the same as a size of the first pad, wherein the first pad includes a first recess configured to receive a first electrode of a passive element, wherein the second pad includes a second recess receiving a second electrode of the passive element, wherein the first recess has a depth substantially the same as a thickness of the first pad, wherein the second recess has a depth substantially the same as a thickness of the second pad, wherein each of the first recess and the second recess exposes an upper surface of the insulation substrate.