Abstract: Provided is a connection structure for a semiconductor package which includes: a first passivation layer having an opening; a first conductive pattern that penetrates the first passivation layer and protrudes upwardly from the first passivation layer; a second passivation layer on the first passivation layer and covering the first conductive pattern; a second conductive pattern on the second passivation layer and electrically connected to the first conductive pattern; a third passivation layer on the second passivation layer and covering the second conductive pattern; and an external terminal in the opening and electrically connected to the first conductive pattern, wherein the first conductive pattern is thicker than the second conductive pattern.

Abstract: A lamination circuit board structure lamination circuit board structure includes a printed circuit board substrate including conductive wiring traces on at least a first wiring face, a prepreg layer formed over the first wiring face, and a patch having an area smaller than 1,000 mm2. The patch includes conductive wiring traces formed on a wiring face and is laminated to the printed circuit board substrate over the prepreg layer, oriented with the wiring face in contact with and pressed into the prepreg layer. Portions of the prepreg layer fill interstices between the conductive wiring traces.

Abstract: An electronic component includes a glass base in which through holes are formed passing through both surfaces thereof; an insulating resin layer laminated on each of both surfaces of the glass base and including a copper plated layer formed therein; and a capacitor including a lower electrode formed on the copper plated layer, a dielectric layer laminated on the lower electrode, and an upper electrode laminated on the dielectric layer. In the electronic component, the upper electrode has a region that is parallel to the copper plated layer and is formed so as to be smaller than a region of the dielectric layer parallel to the surface of the copper plated layer or a region of the lower electrode parallel to the surface of the copper plated layer.

Abstract: An electronic device is provided. The electronic device includes: a substrate, wherein the substrate has a normal direction; a first bonding pad and a second bonding pad disposed side by side on the substrate. The first bonding pad includes a first conductive layer and a second conductive layer, and the first conductive layer is adjacent to the second conductive layer. The second bonding pad includes a third conductive layer, the third conductive layer is adjacent to the second conductive layer, and in the normal direction, a distance between a bottom surface of the third conductive layer and the substrate is different than a distance between a bottom surface of the second conductive layer and the substrate. Viewed from the normal direction of the substrate, at least part of the second conductive layer is between the first conductive layer and the third conductive layer.

Abstract: A resin multilayer substrate includes a stacked body including a first main surface, a cavity provided in the first main surface, and conductor patterns provided in the stacked body. The stacked body includes insulating substrate layers including resin as a main material that are stacked. The cavity includes a side surface and a bottom surface. At least a portion of a boundary between the side surface and the bottom surface includes conductor patterns continuous with the side surface and the bottom surface.

Abstract: A wiring substrate includes a core layer, first conductor layers including a first inner conductor layer, a first outer conductor layer and a first intermediate conductor layer, second conductor layers including a second inner conductor layer, a second outer conductor layer and a second intermediate conductor layer, and interlayer insulating layers interposed between the first conductor layers and between the second conductor layers. The first and/or second inner conductor layers has a first laminated structure including a metal foil layer and a plating film layer, the first and/or second outer conductor layers has the first laminated structure, and the first and/or second intermediate conductor layers has a second laminated structure including a metal foil layer and a plating film layer and includes a conductor pattern formed such that an upper surface of the conductor pattern has an edge portion forming an inclined portion inclined toward the core layer.

Abstract: A component carrier and a method for manufacturing a component carrier is described wherein the component carrier includes a carrier body with a plurality of electrically conductive layer structures and/or electrically insulating layer structures and a wiring structure on and/or in the layer structures where the wiring structure is at least partially formed as a three-dimensionally printed structure.

Abstract: A printed circuit board includes: a first insulating layer; a first wiring layer at least partially buried in the first insulating layer; a second insulating layer disposed on an upper surface of the first insulating layer; a second wiring layer at least partially buried in the second insulating layer; and a cavity penetrating through the second insulating layer and a portion of the first insulating layer and exposing a portion of the upper surface of the first insulating layer as a bottom surface of the cavity. The first wiring layer includes a wiring pattern at least partially exposed from the first insulating layer by the cavity, an upper surface of the wiring pattern has a step structure with the upper surface of the first insulating layer exposed by the cavity, and a lower surface of the wiring pattern is coplanar with a lower surface of the first insulating layer.

Abstract: A printed circuit board includes an electronic component including a first base and a plurality of first lands, the first base including a first main surface, the plurality of first lands being disposed around a first portion of the first main surface and spaced from each other, a printed wiring board including a second base and a plurality of second lands, the second base including a second main surface, the plurality of second lands being disposed around a second portion of the second main surface and spaced from each other, bonding portions configured to bond the first lands and the second lands, a resin portion configured to cover the bonding portions and including cured thermosetting resin, and a member having a property to repel uncured thermosetting resin and disposed on one of the first portion and the second portion.

Abstract: A method for fabricating an assemble substrate is provided, including stacking a circuit portion on a plurality of circuit members. The circuit members are spaced apart from one another in a current packaging process to increase a layer area. The assemble substrate thus fabricated meets the requirements for a packaging substrate of a large size, and has a high yield and low fabrication cost.

Abstract: A wiring structure and a method for manufacturing the same are provided. The wiring structure includes a conductive structure and at least one conductive through via. The conductive structure includes a plurality of dielectric layers, a plurality of circuit layers in contact with the dielectric layers, and a plurality of dam portions in contact with the dielectric layers. The dam portions are substantially arranged in a row and spaced apart from one another. The conductive through via extends through the dam portions.

Abstract: A conductive trace interconnect tape for use with a printed circuit board or a flexible circuit substrate comprises a top insulating layer, an electrically conductive layer, and a bottom insulating layer. The top insulating layer is formed from electrically insulating material and is configured to provide electrical isolation from electrically conductive objects that are positioned on top of the conductive trace interconnect tape. The electrically conductive layer is positioned underneath the top insulating layer. The electrically conductive layer is formed from electrically conductive material and includes electrical interconnect traces, electrical component pads, or electrically conductive planar portions. The bottom insulating layer is positioned underneath the electrically conductive layer.

Abstract: Certain aspects of the present disclosure generally relate to an embedded trace substrate having at least two different dielectric layers with different dielectric materials and methods for fabricating the same. One example embedded trace substrate generally includes a first metal layer; a first dielectric layer disposed below the first metal layer and comprising a first dielectric material; a second dielectric layer disposed below the first dielectric layer and comprising a second dielectric material, wherein the second dielectric material of the second dielectric layer is stiffer than the first dielectric material of the first dielectric layer; and a second metal layer disposed below the second dielectric layer.

Abstract: A component carrier includes a stack having at least one electrically conductive layer structure and/or at least one electrically insulating layer structure; a component embedded in the stack so that a gap of less than 100 ?m, in particular less than 60 ?m, remains between at least one sidewall of the component and a sidewall of an adjacent one of the layer structures or a further component embedded in the stack; and a filler medium including filler particles, wherein the filler medium at least partially fills the gap. In addition, a method of manufacturing a component carrier is provided.

Abstract: A flexible printed circuit board according to the present disclosure includes: a first base sheet, a second base sheet, and a first protection sheet. The first base sheet includes a first Teflon film and a first circuit pattern disposed on the first Teflon film. The second base sheet includes a second Teflon film and a second circuit pattern disposed on the second Teflon film, and is laminated on the first base sheet. The first protection sheet covers the first base sheet. A portion of the first base sheet that is exposed to the first protection sheet is surface-modified.

Abstract: Systems, apparatus, methods for manufacturing and techniques for interconnecting integrated circuit devices are disclosed. A flexible printed circuit (FPC) provides EMI shielding with reduced insertion loss. The FPC includes a first signal layer fabricated from a planar conductive material and having traces configured to carry signals between a circuit boards. The FPC may include a first non-conductive layer disposed in a plane above the first signal layer, a second non-conductive layer disposed in a plane below the first signal layer, a first copper ground plane disposed in a plane above the first non-conductive layer, a second copper ground plane disposed in a plane below the second non-conductive layer, and a second signal layer provided in a plane above the first copper ground plane or below the second copper ground plane. Signals carried in the first signal layer may have a higher frequency than signals carried in the second signal layer.

Abstract: A circuit board includes a plurality of signal contact pads each electrically contacting a contact point of one of a plurality of signal terminals and a non-conductive through hole extending through the circuit board in an interval area between a pair of adjacent signal contact pads of the plurality of signal contact pads.

Abstract: A component carrier with a rigid portion, a flexible portion, a cavity defining the flexible portion next to the rigid portion, and at least one step in a transition portion between the rigid portion and the flexible portion in the cavity is disclosed.

Abstract: A flexible printed circuit board includes: an electrically insulating substrate layer; an electrically conductive pattern stacked on at least one surface of the substrate layer; and a cover layer that is disposed on a stack including the substrate layer and the electrically conductive pattern and covers a surface of the stack, which surface is on the side on which the electrically conductive pattern is present. The electrically conductive pattern has a coil region including a coil. In the substrate layer or the cover layer, a high-magnetic permeability member is present in at least a region that overlaps the coil region in plan view.

Abstract: An electronic assembly is provided, including a wiring board, a control element, and a pair of first internal electrical connectors. The wiring board includes a mounting surface, a first patterned conductive layer, a plurality of second patterned conductive layers, a plurality of near conductive holes, a plurality of far conductive holes, and a first conductive path. The first patterned conductive layer is located between the mounting surface and the second patterned conductive layers. The control element is mounted on the mounting surface of the wiring board. The pair of first internal electrical connectors are mounted on the mounting surface of the wiring board, and are adapted for mounting a pair of memory modules. The first conductive path extends from the control element at least through the corresponding second patterned conductive layer and the first patterned conductive layer to the pair of first internal electrical connectors.