Patents Examined by Ishwarbhai Patel
  • Patent number: 8541691
    Abstract: A circuit wiring board including a wiring substrate, multiple electronic components provided on a surface of the wiring substrate, and a heat resistant substrate accommodated in the wiring substrate and having a core substrate and a built-up wiring layer formed over the core substrate. The built-up wiring layer includes a conductive layer and an interlayer resin insulating layer, and the electronic components are electrically connected to the conductive layer of the built-up wiring layer.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: September 24, 2013
    Assignee: IBIDEN Co., Ltd.
    Inventors: Takashi Kariya, Toshiki Furutani, Takeshi Kawanishi
  • Patent number: 8541695
    Abstract: A wiring board includes a substrate having first and second surfaces, a first penetrating hole penetrating through the substrate, a first through-hole conductor formed on the inner wall of the first hole, a filler filled inside the first conductor and forming a second penetrating hole, and a second through-hole conductor formed in the second hole, a first conductive circuit on the first surface of the substrate, a second conductive circuit on the second surface of the substrate, a first conductive portion on one end of the second hole, and a second conductive portion on the opposite end of the second penetrating hole. The first conductor is connecting the first circuit and the second circuit. The second conductor is made of a conductive material filled in the second hole and is connecting the first conductive portion and the second conductive portion.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: September 24, 2013
    Assignee: Ibiden Co., Ltd.
    Inventors: Atsushi Ishida, Ryojiro Tominaga, Kenji Sakai
  • Patent number: 8536464
    Abstract: A multilayer substrate is provided with a conductor plane region in which a plurality of conductor planes are disposed; a clearance region disposed adjacent to the conductor plane region so that the plurality of conductor planes are excluded from the clearance region. A plurality of signal vias are disposed through the clearance region so that the plurality of signal vias are isolated from the plurality of conductor planes. A conductor post is connected to one of the plurality of conductor planes and disposed between two of the signal vias in the clearance region.
    Type: Grant
    Filed: May 26, 2008
    Date of Patent: September 17, 2013
    Assignee: NEC Corporation
    Inventors: Taras Kushta, Jun Sakai, Hikaru Kouta
  • Patent number: 8525041
    Abstract: A wiring board has a substrate, a conductive pattern formed over the substrate, and an electronic component mounted to the substrate and having an electrode. The electrode of the electronic component is connected to the conductive pattern through a via hole. The thickness of the electrode of the electronic component is made less than the thickness of the conductive pattern.
    Type: Grant
    Filed: August 19, 2009
    Date of Patent: September 3, 2013
    Assignee: Ibiden Co., Ltd.
    Inventors: Keisuke Shimizu, Yoichiro Kawamura
  • Patent number: 8525035
    Abstract: Disclosed is a double-side-conducting flexible-circuit flat cable with cluster section, which includes a flexible circuit substrate, a first electrical conduction path, a second electrical conduction path, a plurality of first and second conductive contact zones. The flexible circuit substrate has a first surface and a second surface and includes, in an extension direction, a first connection section, a cluster section, and at least one second connection section. The cluster section is composed of a plurality of clustered flat cable components formed by slitting in the extension direction. The first and second electrical conduction paths are respectively formed on the first and second surfaces of the flexible circuit substrate and each extends along one of the clustered flat cable components of the cluster section. The plurality of first and second conductive contact zones are respectively arranged on the first and second surfaces of the flexible circuit substrate at the first connection section.
    Type: Grant
    Filed: October 15, 2010
    Date of Patent: September 3, 2013
    Assignee: Advanced Flexible Circuits Co., Ltd.
    Inventors: Gwun-Jin Lin, Chih-Heng Chuo, Kuo-Fu Su
  • Patent number: 8525038
    Abstract: A flex-rigid wiring board includes a flexible board including a flexible substrate and a conductor pattern formed over the flexible substrate, a non-flexible substrate disposed adjacent to the flexible board, an insulating layer including an inorganic material and covering the flexible board and the non-flexible substrate, the insulating layer exposing at least one portion of the flexible board, a conductor pattern formed on the insulating layer, and a plating layer connecting the conductor pattern of the flexible board and the conductor pattern on the insulating layer.
    Type: Grant
    Filed: May 20, 2011
    Date of Patent: September 3, 2013
    Assignee: Ibiden Co., Ltd.
    Inventors: Michimasa Takahashi, Masakazu Aoyama
  • Patent number: 8513536
    Abstract: An electronic circuit module is mounted on an electronic circuit board. The electronic circuit module includes an electronic component that has a first electrode and a second electrode that form a facing surface. The electronic circuit module also includes a coaxial cable with a core wire and a shielded wire being exposed in stages. The core wire and the shielded wire of the coaxial cable are directly connected to the first electrode and the second electrode that are exposed at a predetermined cable connecting surface of the electronic component.
    Type: Grant
    Filed: December 1, 2010
    Date of Patent: August 20, 2013
    Assignee: Olympus Corporation
    Inventors: Nau Negishi, Mikio Nakamura
  • Patent number: 8513532
    Abstract: A flexible circuit structure with stretchability comprises a flexible substrate, a metal layer, and a plurality of flexible bumps. The metal layer is formed on the flexible substrate. These flexible bumps are formed on the metal layer and the flexible substrate.
    Type: Grant
    Filed: February 23, 2011
    Date of Patent: August 20, 2013
    Assignee: Industrial Technology Research Institute
    Inventors: Yu-Hua Chen, Ying-Ching Shih
  • Patent number: 8507806
    Abstract: A circuit wiring board including a wiring substrate, and a heat resistant substrate accommodated in the wiring substrate and including a core substrate and a through hole conductor formed in the core substrate, the core substrate having a first surface and a second surface on an opposite side of the first surface, the through hole conductor providing electrical connection through the core substrate between the first surface and the second surface of the core substrate.
    Type: Grant
    Filed: June 19, 2009
    Date of Patent: August 13, 2013
    Assignee: IBIDEN Co., Ltd.
    Inventors: Takashi Kariya, Toshiki Furutani, Takeshi Kawanishi
  • Patent number: 8502084
    Abstract: A semiconductor chip carrier having multiple conductive layers separated from each other by dielectric layers, a chip bonding position at an intermediate portion of a top surface of the semiconductor chip carrier, and a bonding region spaced apart from the chip bonding position. The bonding region includes a first bonding region closest to the chip bonding position, a second bonding region most distant from the chip bonding position, and a third bonding region positioned between the first bonding region and the second bonding region. The first bonding region, the second bonding region and the third bonding region are electrically insulated from each other and the first bonding region is configured to carry a first voltage, the second bonding region is configured to carry a second voltage and the third bonding region is configured to carry a third voltage that is less than the first voltage and less than the second voltage.
    Type: Grant
    Filed: May 3, 2010
    Date of Patent: August 6, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun seok Song, Hee seok Lee, Hyun-a Kim, So-young Lim
  • Patent number: 8492657
    Abstract: A board interconnection structure having a first printed wiring board in which a first conductive circuit is arranged on a first insulating layer, the first conductive circuit having, on an end portion thereof, a first connection terminal in which an upper surface width is narrower than a bottom surface width; a second printed wiring board in which a second conductive layer having a second connection terminal is arranged on a second insulating layer; and a connection layer that forms fillets along longitudinal side surfaces of the first connection terminal, and interconnects the first connection terminal and the second connection terminal. The first connection terminal may have a projection portion.
    Type: Grant
    Filed: July 21, 2010
    Date of Patent: July 23, 2013
    Assignee: Fujikura Ltd.
    Inventors: Tomofumi Kitada, Hiroki Maruo, Ryo Takami
  • Patent number: 8492659
    Abstract: The present invention provides a printed wiring board which can prevent a plating failure in a connection hole such as a via to be formed in the printed wiring board, thereby can enhance the connection reliability and a manufacturing method therefor. The printed wiring board 100 includes a thermosetting resin sheet 16 (insulation layer) having a via hole 20 (through hole) constituted by inner wall parts having different taper angles from each other, a copper foil 17 (conductor layer) provided on the thermosetting resin sheet 16, and a wiring pattern 13 (wiring layer) which is provided so as to be exposed from the via hole 20 and is electrically connected with the copper foil 17 through the via hole 20.
    Type: Grant
    Filed: February 18, 2009
    Date of Patent: July 23, 2013
    Assignee: TDK Corporation
    Inventors: Kenji Nagase, Hiroyuki Uematsu, Kenichi Kawabata
  • Patent number: 8487194
    Abstract: The document describes a circuit board and an electronic module, including a conductor-pattern layer, an insulating-material layer supporting the conductor-pattern layer, and at least one component inside the insulating-material layer. The component has a plurality of contact areas and the circuit board or electronic module includes contact elements between the conductor-pattern layer and contact areas for electrically connecting the conductor-pattern layer and the at least one component such that at least two of the contact elements are in direct contact with a common contact area.
    Type: Grant
    Filed: February 9, 2010
    Date of Patent: July 16, 2013
    Assignee: Imbera Electronics Oy
    Inventors: Risto Tuominen, Petteri Palm
  • Patent number: 8487195
    Abstract: A via structure is disclosed to pass electronic signals from a first conductive pathway formed on a first outermost substrate of a multi-layer PCB to a second conductive pathway formed on a second outermost substrate of the multi-layer PCB. The via structure allows the electronic signals to pass from the first outermost substrate through one or more inner substrates to the second outermost substrate. The one or more inner substrates include one or more closed geometric structures to enclose the via structure.
    Type: Grant
    Filed: March 4, 2010
    Date of Patent: July 16, 2013
    Assignee: Broadcom Corporation
    Inventor: Shengli Lin
  • Patent number: 8481862
    Abstract: The present invention relates to a connector system for resiliently attaching and electrically connecting an integrated circuit chip to a circuit board using a plurality of leads. Each of the plurality of leads are sized and arranged to form a curved body having a first leg and a second leg with a curved portion between the first leg and the second leg. The curved body of the leads may be C-shaped in accordance with the present invention. The plurality of leads may be formed from strips of copper foil or copper mesh folded to form the curved body. The plurality of leads may also be sized and arranged to support the integrated circuit chip in a generally flat arrangement relative to the circuit board with a maximum separation of about 0.016 inches or less between the integrated circuit chip and the circuit board.
    Type: Grant
    Filed: February 9, 2006
    Date of Patent: July 9, 2013
    Assignee: General Dynamics Advanced Information Systems, Inc.
    Inventors: Deepak K. Pai, Melvin Eric Graf
  • Patent number: 8476533
    Abstract: An exemplary printed circuit board includes a substrate, a differential transmission line, and at least two weld pad pairs. The differential transmission line and the at least two weld pad pairs are disposed on the substrate. The differential transmission line includes two parallel signal conductors disposed on the substrate. Each of the two signal conductors is electrically connected to an edge of one of the weld pads of a respective pair of the at least two weld pad pairs. Thereby, the two signal conductors of the differential transmission line can extend in the same distance anywhere, particularly in the position where the two signal conductors pass the two weld pad pairs. As a result, the coupling performance and the capability of the differential transmission line to resist electromagnetic interference are both enhanced.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: July 2, 2013
    Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.
    Inventor: Fa-Ping Fan
  • Patent number: 8476535
    Abstract: A multilayered printed wiring board includes a flexible wiring board with wiring layers on both main surfaces thereof; a rigid wiring board with wiring layers on both main surfaces thereof and formed opposite to the flexible wiring board under the condition that an area of the main surface of the rigid wiring board is smaller than an area of the main surface of the flexible wiring board; and an electric/electronic component embedded in the rigid wiring board.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: July 2, 2013
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Takahiro Sahara, Atsushi Kobayashi, Masahiko Igaue, Kiyoshi Takeuchi
  • Patent number: 8471154
    Abstract: A stackable variable height via package includes a substrate having a first surface and terminals thereon. The terminals include a first terminal and a second terminal. Vias are on the terminals, the vias including a first via on the first terminal and a second via on the second terminal. The first via has a height from the first surface of the substrate less than a height of the second via from the first surface of the substrate. The package further includes a package body and via apertures in the package body to expose the vias. Forming the stackable variable height via package with variable height vias readily accommodate stacking of additional packages having different types of terminals, e.g., LGA and BGA type packages, as well as variable degrees of warpage on the stackable variable height via package. Further, the vias are formed with a minimum pitch.
    Type: Grant
    Filed: August 6, 2009
    Date of Patent: June 25, 2013
    Assignee: Amkor Technology, Inc.
    Inventors: Akito Yoshida, Mahmoud Dreiza
  • Patent number: 8466369
    Abstract: A circuit structure of a circuit board includes a dielectric layer, a number of first circuits, and a number of second circuits. The dielectric layer has a surface and an intaglio pattern. The first circuits are disposed on the surface of the dielectric layer. The second circuits are disposed in the intaglio pattern of the dielectric layer. Line widths of the second circuits are smaller than line widths of the first circuits, and a distance between every two of the adjacent second circuits is shorter than a distance between every two of the adjacent first circuits.
    Type: Grant
    Filed: November 28, 2011
    Date of Patent: June 18, 2013
    Assignee: Unimicron Technology Corp.
    Inventor: Cheng-Po Yu
  • Patent number: 8466371
    Abstract: An interconnecting structure for interconnecting two electronic modules. The structure includes a dielectric substrate having a copper trace deposited on the lower surface thereof, and a copper pad disposed on the upper surface of the substrate directly above one end of the trace. A first copper plate-up area deposited on the pad, and a second copper plate-up area is deposited on the distal end of the trace. A slot, semi-circumscribing the pad and extending on both sides of the trace toward the distal end of the trace, is cut through the substrate to allow the proximal end of the trace to be displaced in a cantilevered manner below the lower side of the substrate when a force is applied to the pad.
    Type: Grant
    Filed: November 10, 2008
    Date of Patent: June 18, 2013
    Inventor: Erick Spory