Abstract: At least one redistribution layer (RDL) is provided on a silicon die. A passivation layer is deposited on the RDL. First openings having a first diameter are etched in the passivation layer where copper posts are to be formed. A seed layer is deposited over the passivation layer and within the openings. A photoresist layer is coated on the seed layer and patterned to form second openings having a second diameter over the first openings larger than the first diameter. Copper is plated on the seed layer to form copper posts filling the second openings. The silicon die is die attached to a metal substrate. A lamination layer is coated over the silicon die and the copper posts. Third openings are formed through the lamination layer to the copper posts and to metal pads on the metal substrate. Metal vias are formed in the third openings.

Abstract: The present disclosure discloses a micro-LED transfer method, a manufacturing method, device and an electronic apparatus. The transfer method comprises: in accordance with a sequence of micro-LEDs of blue, green and red, epitaxially growing micro-LEDs of two or all of the three colors on a single GaAs original substrate; epitaxially growing bumping electrodes corresponding to the micro-LEDs on a receiving substrate; bonding the micro-LEDs of the two or all of the three colors with the bumping electrodes on the receiving substrate; and removing the GaAs original substrate. The method can be used to transfer micro-LEDs of a variety of colors, in order to improve the production efficiency.

Abstract: The present disclosure provides an interconnect structure, including a first metal line, a conductive contact over the first metal line, including a first portion, a second portion over the first portion, wherein a bottom width of the second portion is greater than a top width of the first portion, and a third portion over the second portion, wherein a bottom width of the third portion is greater than a top width of the second portion, a sacrificial bilayer, including a first sacrificial layer, wherein a first portion of the first sacrificial layer is under a coverage of a vertical projection area of the first portion of the conductive contact, and a second sacrificial layer over the first sacrificial layer, and a dielectric layer over a top surface of the second sacrificial layer.

Abstract: A manufacturing method of a split gate structure includes steps of forming a mask oxide layer on the substrate, performing photolithography and etching on the mask oxide layer and the substrate, forming a trench, removing the mask oxide layer, forming a bottom oxide layer on a bottom part and a side wall of the trench and a surface of the substrate, forming a silicon nitride layer on the trench, removing a part of the bottom oxide layer, forming a gate oxide layer on part of the side wall and the surface, forming a gate poly layer on the trench, removing the silicon nitride layer, forming an inter-poly oxide layer on the gate poly layer, and forming a shield poly layer on the trench, thereby benefiting the increasing of the thickness of the inter-poly oxide layer, so that the advantages of improving the characteristics of the split gate structure are achieved.

Abstract: A semiconductor device including a contact structure is provided. The semiconductor device includes an isolation region defining a lower active region. First and second source/drain regions and first and second gate electrodes are on the lower active region. The first and second source/drain regions are adjacent to each other. First and second gate capping patterns are on the first and second gate electrodes, respectively. First and second contact structures are on the first and second source/drain regions, respectively. A lower insulating pattern is between the first and second source/drain regions. An upper insulating pattern is between the first and second contact structures. Silicon oxide has etching selectivity with respect to an insulating material which the upper insulating pattern, the first gate capping pattern, and the second gate capping pattern are formed of.

Abstract: A semiconductor device includes a semiconductor module having a heat conductive portion formed of metal and also having a molded resin having a surface at which the heat conductive portion is exposed, a cooling body secured to the semiconductor module by means of bonding material, and heat conductive material formed between and thermally coupling the heat conductive portion and the cooling body.

Abstract: A display device includes a first pixel, a second pixel, and a third pixel. The common electrodes of the first and second pixels have an integrated shape. The hole control layers of the first and second pixels have an integrated shape. The electron control layers of the first and second pixels have an integrated shape. The common electrode, the hole control layer or the electron control layer of the third pixel may be separated from the first pixel and the second pixel.

Abstract: In a general aspect, a packaged semiconductor device apparatus a conductive paddle, a semiconductor die coupled with the conductive paddle and a conductive clip having a first portion with a first thickness and a second portion with a second thickness. The first thickness can be greater than the second thickness. The first portion can be coupled with the semiconductor die. The device can also include a molding compound encapsulating the semiconductor die and at least partially encapsulating the conductive paddle and the conductive clip. The device can further include a signal lead that is at least partially encapsulated in the molding compound, the second portion of the conductive clip being coupled with the signal lead.

Abstract: A display device comprises a substrate provided with a first subpixel area and a second subpixel area, a first electrode provided on the substrate, including a first sub electrode provided in the first subpixel area and a second sub electrode provided in the second subpixel area, an organic light emitting layer including a first organic light emitting layer arranged on the first sub electrode and a second organic light emitting layer arranged on the second sub electrode, and a second electrode arranged on the organic light emitting layer, wherein the first organic light emitting layer includes a first pattern layer, a second pattern layer provided on the first pattern layer and a third pattern layer provided on the second pattern layer, the second organic light emitting layer includes a first pattern layer, a second pattern layer provided on the first pattern layer and a third pattern layer provided on the second pattern layer, the first pattern layer of the first organic light emitting layer is spaced apart

Abstract: A light emitting device comprising a coating layer is disclosed. A reflective layer is on a base. A structure on the reflective layer has a first opening there through. The first opening exposes a surface of the reflective layer. A light emitting diode (LED) is on the exposed surface of the reflective layer. A coating layer is on the exposed surface of the reflective layer, at least a portion of the structure inside the first opening, and at least a portion of the LED. A second opening is in the coating layer. The second opening exposes a portion of the reflective layer. A conductive element electrically couples the LED to the base through the portion of the reflective layer exposed by the second opening in the coating layer.

Abstract: A semiconductor device includes a semiconductor die having a main surface, a rear surface, outer edge sides extending between the main and rear surfaces, and a first conductive bond pad disposed on the main surface, an electrically insulating mold compound body formed around the outer edge sides of the semiconductor die with the main surface of the semiconductor die exposed from an upper surface of the mold compound body, a first metallization layer formed on the upper surface of the mold compound body and on the main surface of the semiconductor die, and a first bond pad extension formed in the first metallization layer. The first bond pad extension overlaps with the upper surface of the mold compound body. The first bond pad extension is conductively connected with the first conductive bond pad. The first bond pad extension is an externally accessible point of electrical contact of the device.

Abstract: A method of manufacturing a package, comprising embedding the semiconductor chip with an encapsulant comprising a transition metal in a concentration in a range between 10 ppm and 10,000 ppm; selectively converting of a part of the transition metal, such that the electrical conductivity of the encapsulant increases; and plating the converted part of the encapsulant with an electrically conductive material.

Abstract: A metal oxide semiconductor field effect transistor (MOSFET) includes a substrate having a source region, a drain region, and a channel region between the source region and the drain region, the substrate having an epitaxial III-V material that includes three elements thereon, a source electrode over the source region, a drain electrode over the drain region, and a crystalline oxide layer including an oxide formed on the epitaxial III-V material in the channel region, the epitaxial III-V material including three elements.

Abstract: In accordance with an embodiment, a method for producing a graphene-based sensor includes providing a carrier substrate; forming a carrier structure on the carrier substrate, wherein one or more separating structures are formed on an upper side of the carrier structure; and performing a wet chemical transfer of a graphene layer onto the upper side of the carrier structure that comprises the separating structures, where the separating structures and a tear strength of the graphene layer are matched to one another such that the graphene layer respectively tears at the separating structures during the wet chemical transfer.

Abstract: Package structures are provided. A package structure includes an adhesive layer and a semiconductor substrate over the adhesive layer. The package structure also includes a connector over the semiconductor substrate. The package structure further includes a first buffer layer surrounding the connector. In addition, the package structure includes an encapsulation layer surrounding the first buffer layer. The first buffer layer is sandwiched between the encapsulation layer and the semiconductor substrate, and a sidewall of the encapsulation layer is in direct contact with a sidewall of the first buffer layer and a sidewall of the adhesive layer. The package structure also includes a redistribution layer over the first buffer layer and the encapsulation layer.

Abstract: Systems and methods for improving heat distribution and heat removal efficiency in PoP semiconductor packages are provided. A PoP semiconductor package includes a first semiconductor package that is physically, communicably, and conductively coupled to a stacked second semiconductor package. A gap forms between the upper surface of the first semiconductor package and the lower surface of the second semiconductor package. Additionally, interstitial gaps form between each of the PoP semiconductor packages disposed on an organic substrate. A curable fluid material, such as a molding compound, may be flowed both in the interstitial spaces between the PoP semiconductor packages and into the gap between the upper surface of the first semiconductor package and the lower surface of the second semiconductor package.

Abstract: An Antenna-in-Package (AiP) includes an interface layer having at least an antenna layer and an insulating layer disposed under the antenna layer. The antenna layer includes a first antenna region and a second antenna region spaced apart from the first antenna region. An integrated circuit die is disposed on the interface layer. The integrated circuit die is interposed between the first antenna region and the second antenna region. The first antenna region includes a first antenna element, a second antenna element extending along a first direction, and a feeding network electrically connecting the first antenna element and the second antenna element to the integrated circuit die. The feeding network, the first antenna element, and the second antenna element are coplanar. A plurality of solder balls is disposed on a surface of the interface layer.

Abstract: A method for forming a semiconductor device includes forming a barrier layer over a dielectric layer, a concentration of an impurity in the barrier layer increasing as the barrier layer extends away from the dielectric layer; and performing a plasma process to treat the barrier layer.

Abstract: A semiconductor component includes gate structures extending into a silicon carbide body from a first surface. A width of the gate structures along a first horizontal direction parallel to the first surface is less than a vertical extent of the gate structures perpendicular to the first surface. Contact structures extend into the silicon carbide body from the first surface. The gate structures and the contact structures alternate along the first horizontal direction. Shielding regions in the silicon carbide body adjoin a bottom of the contact structures and are spaced apart from the gate structures along the first horizontal direction. Corresponding methods for producing the semiconductor component are also described.

Abstract: A multi-color LED display comprises pixels, each comprising a first sub-pixel, a second sub-pixel, and a third sub-pixel. The first sub-pixel comprises a first light-emitting diode (LED) that emits a first color of light, the second sub-pixel comprises second LEDs that emit a second color of light different from the first color of light, and the third sub-pixel comprises third LEDs that emit a third color of light different from the first color of light and different from the second color of light. The second LEDs are electrically connected in parallel and the third LEDs are electrically connected in series.