Abstract: A purpose of the present invention is to provide a semiconductor device that can restrain occurrence of partial discharge in evaluation of electric characteristics and can carry out failure analysis from the upper side of a measurement object. A semiconductor device according to the present invention includes: at least one electrode; a protective layer having at least one opening part provided such that a portion of the electrode is exposed at the opening part, and being formed to cover the other portion of the electrode excluding the portion of the electrode exposed at the opening part, the protective layer being insulative; and a conductive layer formed so as to cover the protective layer and the opening part and be directly connected to the electrode at the opening part.

Abstract: According to one embodiment, a display device includes a first substrate including as insulating substrate with a first through hole, a pad electrode positioned above the insulating substrate, and a signal line electrically connected to the pad electrode, a second substrate opposed to the first substrate, a sealant which adheres the first substrate and the second substrate, a line substrate including a connection line and disposed below the insulating substrate, and a conductive material which electrically connects the pad electrode and the connection line, wherein the sealant is less absorptive than is the insulating substrate as to a wavelength less than 350 nm.

Abstract: Semiconductor devices, such as transistors, FETs and HEMTs having a non-linear gate foot region and non-linear channel width are disclosed as well as methods of making and using such devices and the operational benefits of the devices.

Abstract: A light-emitting device includes a carrier with a first surface and a second surface opposite to the first surface; and a light-emitting unit disposed on the first surface and configured to emit a light toward but not passing through the first surface. When emitting the light, the light-emitting device has a first light intensity above the first surface, and a second light intensity under the second surface, a ratio of the first light intensity to the second light intensity is in a range of 2˜9.

Abstract: A semiconductor device including a contact structure is provided. The semiconductor device includes an isolation region defining a lower active region. First and second source/drain regions and first and second gate electrodes are on the lower active region. The first and second source/drain regions are adjacent to each other. First and second gate capping patterns are on the first and second gate electrodes, respectively. First and second contact structures are on the first and second source/drain regions, respectively. A lower insulating pattern is between the first and second source/drain regions. An upper insulating pattern is between the first and second contact structures. Silicon oxide has etching selectivity with respect to an insulating material which the upper insulating pattern, the first gate capping pattern, and the second gate capping pattern are formed of.

Abstract: A tunneling field-effect transistor with an insulated planar gate adjacent to a heterojunction between wide-bandgap semiconductor, such as silicon carbide, and either a narrow band gap material or a high work function metal. The heterojunction may be formed by filling a recess on a silicon carbide planar substrate, for example by etched into an epitaxially grown drift region atop the planar substrate. The low band gap material may be silicon which is deposited heterogeneously and, optionally, annealed via laser treatment and/or doped. The high work function metal may be tungsten, platinum, titanium, nickel, tantalum, or gold, or an alloy containing such a metal. The plane of the gate may be lateral or vertical. A blocking region of opposite doping type from the drift prevents conduction from the filled recess to the drift other than the conduction though the heterojunction.

Abstract: A method of processing a semiconductor wafer includes forming a plurality of die in the semiconductor wafer. The semiconductor wafer has a first brittleness. The top surface the semiconductor wafer undergoes grinding to leave an inner planar surface and a rim, wherein the rim extends above the inner planar surface and around a perimeter of the grinded semiconductor wafer. The first encapsulant material is formed over the inner planar surface and contained within the rim to form a composite semiconductor wafer that has a second brittleness less than the first brittleness. The composite semiconductor wafer is singulated into the plurality of die in which each die of the plurality of die is a composite structure die.

Abstract: An oxide thin-film transistor, an array substrate and methods for manufacturing the same, and a display device are provided. The method for manufacturing the oxide thin-film transistor includes: forming a pattern of an oxide semi-conductor layer above a base substrate; and illuminating, by a light source, two opposite boundary regions of the pattern of the oxide semi-conductor layer, where the illuminated two opposite boundary regions of the pattern of the oxide semi-conductor layer form ohmic contact layers and a region of the pattern of the oxide semi-conductor layer that is not illuminated forms a semi-conductor active layer; forming a source electrode and a drain electrode which are connected to the semi-conductor active layer via the ohmic contact layers respectively.

Abstract: In a method of manufacturing an MRAM device, a lower electrode and a preliminary first free layer pattern sequentially stacked are formed on a substrate. An upper portion of the preliminary first free layer pattern is removed to form a first free layer pattern. A second free layer and a tunnel barrier layer are sequentially formed on the first free layer pattern. The second free layer is partially oxidized to form a second free layer pattern. A fixed layer structure is formed on the tunnel barrier layer.

Abstract: A method of manufacturing a semiconductor device includes: (a) loading into a process chamber a substrate including: a wiring layer including a first interlayer insulating film, a plurality of copper-containing films formed on the first interlayer insulating film and used as a wiring, an inter-wire insulating film electrically insulating the plurality of copper containing film and a recess formed between the plurality of copper-containing film; and a first diffusion barrier film formed on a first portion of a surface of the plurality of copper-containing films to suppress a diffusion of a component of the plurality of copper-containing film; and (b) supplying a silicon-containing gas into the process chamber to form a silicon-containing film on: a surface of the recess; and a second portion of the surface of the plurality of copper-containing films other than the first portion where the first diffusion barrier film is formed.

Abstract: A pixel structure including an active device, a first protection layer, a first electrode, an isolator, a second protection layer and a second electrode is provided. The active device includes a gate, a source and a drain. The first protection layer covers the active device and has a first opening above the drain. The first electrode is disposed above the first protection layer. The first electrode has a side wall corresponding to the first opening. The isolator covers the side wall of the first electrode. The second protection layer covers the first electrode. The second electrode is disposed on the second protection layer, electrically connected to the drain through the first opening, and electrically isolated from the first electrode by the second protection layer and the isolator.

Abstract: An optoelectronic semiconductor chip including a multi-quantum well including at least one high barrier layer is disclosed. In an embodiment, the chip includes a p-type semiconductor region, an n-type semiconductor region and an active layer suitable for emission of radiation arranged between the p-type region and the n-type region, wherein the active layer is in the form of a multiple quantum well structure. The multiple quantum well structure has a plurality of alternating quantum well layers and barrier layers, wherein a barrier layer arranged closer to the p-type region than to the n-type region is a high barrier layer having an electronic band gap Ehb that is larger than electronic band gaps Eb of other barrier layers, and wherein a quantum well layer that adjoins the high barrier layer on a side facing towards the p-type region has a thickness that is greater than thicknesses of other quantum well layers.

Abstract: Described is an optoelectronic semiconductor chip (1) with a built-in bridging element (9, 9A) for overvoltage protection.

Abstract: A power electronics assembly having a semiconductor device that includes a first device surface opposite a second device surface, a semiconductor substrate layer that extends from the first device surface to a substrate-drift interface, a semiconductor drift layer that extends from the substrate-drift interface towards the second device surface, and a semiconductor fluid channel is positioned within the semiconductor substrate layer of the semiconductor device. Further, the semiconductor fluid channel includes an inner surface. Moreover, a fluid channel metallization layer is positioned along the inner surface of the semiconductor fluid channel.

Abstract: The invention relates to an optoelectronic semiconductor chip (10) comprising a carrier (2) and a semiconductor body (1) having an active layer (13) provided for generating electromagnetic radiation. Said carrier (2) has a first main surface (2A) facing the semiconductor body, a second main surface (2B) facing away from the semiconductor body, and a sidewall (2C) arranged between the first main surface and the second main surface. The carrier (2) has a structured region (21, 22, 23, 2C) for enlarging the total surface area of the sidewall, wherein the structured region has singulation traces. The invention also relates to an optoelectronic component (100) comprising such a semiconductor chip and a method for producing a plurality of such semiconductor chips are specified.

Abstract: A method of manufacturing an integrated circuit device includes providing a substrate with a pattern structure, the pattern structure including a plurality of first patterns that extend in a first direction, are parallel to one another, and are separated from one another with a space therebetween. At least one support structure that contacts an upper surface of the pattern structure and extends on the pattern structure in a second direction that crosses the first direction is formed. A buried layer that fills the spaces between the plurality of first patterns while the at least one support structure contacts the upper surface of the pattern structure is formed. The at least one support structure is separated from the pattern structure.

Abstract: A system and method for stacking semiconductor devices in three dimensions is provided. In an embodiment two or more semiconductor dies are attached to a carrier and encapsulated. Connections of the two or more semiconductor dies are exposed, and the two or more semiconductor dies may be thinned to form connections on an opposite side. Additional semiconductor dies may then be placed in either an offset or overhanging position.

Abstract: Electrode arrays for biological implants are disclosed. Electrodes are arranged in such a way so that electrical traces overlap other electrical traces in a separate layer without X shaped crossing, while overlapping to a degree sufficient to prevent dielectric breakdown of the insulating, separating layer.

Abstract: A semiconductor device includes a first well disposed in a substrate and including a first impurity of a first conductivity type, a second well disposed in the substrate, including a second impurity of a second conductivity type different from the first conductivity type, and having first to third portions, and a gate structure formed on the first well and the second well, wherein the second portion is disposed between the first portion and the third portion, the first portion and the third portion are formed deeper than the second portion, and concentration of the second impurity of the first portion and the third portion is greater than concentration of the second impurity of the second portion.

Abstract: An insulated gate bipolar transistor (100) is provided. A substrate (10) of the insulated gate bipolar transistor (100) is of an N type. A P-type region (16) is disposed on a back of the N-type substrate. A back metal structure (18) is disposed on a back of the P-type region (16). A terminal protection ring is disposed in a terminal structure. A polysilicon gate (31) is disposed on a front surface of the substrate (10) in an active region. Sidewalls (72) are disposed at two sides of the polysilicon gate (31) on the substrate (10). An interlayer medium (81) covered with the polysilicon gate (31) and the sidewalls (72) is disposed on the substrate (10). The interlayer medium (81) is covered with a metal lead wire layer (91). An N-type carrier enhancement region (41) is disposed in the substrate (10) in the active region. A P-type body region (51) is disposed in the carrier enhancement region (41). An N-type heavily doped region (61) is disposed in the P-type body region (51).