Patents Examined by Ismail Muse
  • Patent number: 11959606
    Abstract: A package structure including a carrier, a photonic device, a supporting frame, and an encapsulant is provided. The photonic device is disposed on the carrier. The supporting frame is disposed on the carrier and surrounds the photonic device. The encapsulant covers the supporting frame and surrounds the photonic device.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: April 16, 2024
    Assignees: LITE-ON OPTO TECHNOLOGY (CHANGZHOU) CO., LTD., LITE-ON TECHNOLOGY CORPORATION
    Inventors: Chen-Hsiu Lin, Cheng-Ying Lee, Ming-Sung Tsai
  • Patent number: 11961949
    Abstract: Provided are a light emitting device and manufacturing method thereof, a backlight module, a display panel and a display device. The manufacturing method includes: providing a substrate; forming a circuit layer on a side of the substrate; providing at least one switching element and at least one light emitting element; and electrically connecting the switching element and the light emitting element to the circuit layer. The circuit layer includes a first power signal line, a second power signal line, and a pulse width modulation signal line; the switching element includes a control terminal, a first terminal and a second terminal; the light emitting element is electrically connected between the first terminal and the first power signal line, or the light emitting element is electrically connected between the second terminal and the second power signal line.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: April 16, 2024
    Assignee: Shanghai Tianma Micro-Electronics Co., Ltd.
    Inventors: Lihua Wang, Xiaoping Sun, Conghua Ma, Qiang Dong
  • Patent number: 11956974
    Abstract: The invention discloses a memory fabrication method. The memory fabrication method includes forming a plurality of gate electrode lines to respectively form a plurality of gates of a plurality of data storage cells, and forming a plurality of conductive lines. The plurality of data storage cells are arranged in an array. Each of the plurality of conductive lines is coupled to two of the plurality of gate electrode lines. Each of the plurality of conductive lines at least partially overlaps the two gate electrode lines of the plurality of gate electrode lines.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: April 9, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuo-Hsing Lee, Sheng-Yuan Hsueh
  • Patent number: 11942485
    Abstract: A substrate includes a driving backplane, a plurality of first connecting lines and a plurality of second connecting lines. The driving backplane includes a base substrate, at least one first lead group and at least one second lead group. Each first lead group includes a plurality of first leads, and each second lead group includes a plurality of second leads. A first lead group and a corresponding second lead group is disposed in a peripheral region. The plurality of first connecting lines are disposed on at least one side face of the driving backplane, each first connecting line is electrically connected to at least one first lead. The plurality of second connecting lines are disposed on the at least one side face of the driving backplane, each second connecting line is electrically connected to at least one second lead, and is in contact with a corresponding first connecting line.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: March 26, 2024
    Assignees: BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yonglian Qi, Hong Yang, Lianjie Qu, Shan Zhang, Hebin Zhao, Yun Qiu
  • Patent number: 11935993
    Abstract: A stretchable display device according to present disclosure may include a base substrate, a plurality of first substrates on the base substrate, a plurality of second substrates connecting adjacent first substrates, inorganic insulating layers on the first substrates, an organic insulating layer disposed on the first substrates so as to cover top surfaces and side surfaces of the inorganic insulating layers. The device includes first connection lines disposed on the organic insulating layer on the first substrates and disposed on a second substrate extending in a first direction, second connection lines disposed between the inorganic insulating layers and the organic insulating layer on the first substrates and disposed on a second substrate extending in a second direction, and a step alleviating layer disposed between the second connection lines and the inorganic insulating layers.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: March 19, 2024
    Assignee: LG Display Co., Ltd.
    Inventors: Hyeseon Eom, Jonghyeok Im, Doohyun Yoon
  • Patent number: 11935910
    Abstract: Provided is a semiconductor light-emitting device including a substrate, a first insulating layer disposed on an upper surface of the substrate, a plurality of light-emitting structures disposed on the first insulating layer and spaced apart from each other, each of the plurality of light-emitting structures including a first semiconductor layer, an active layer, and a second semiconductor layer, a plurality of optical layers each filling a groove that is formed at a certain depth in the second semiconductor layer, a plurality of first electrodes penetrating the substrate and electrically connected to the first semiconductor layer, a plurality of second insulating layers disposed on side surfaces of each of the plurality of light-emitting structures, respectively, and a second electrode connected to the plurality of light-emitting structures, the second electrode being disposed on an uppermost surface of the second semiconductor layer and each of the plurality of second insulating layers.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: March 19, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jongin Yang, Joosung Kim, Donggun Lee, Suhyun Jo
  • Patent number: 11929320
    Abstract: A device includes a device level having a metallization structure coupled to a semiconductor device and a transistor above the device level. The transistor has a body including a single crystal group III-V or group IV semiconductor material, a source structure on a first portion of the body and a drain structure on a second portion of the body, where the source structure is separate from the drain structure. The transistor further includes a gate structure including a first gate structure portion in a recess in the body and a second gate structure portion between the source structure and the drain structure. A source contact is coupled with the source structure and a drain contact is coupled with the drain structure. The source contact is in contact with the metallization structure in the device level.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: March 12, 2024
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Ryan Keech, Cory Bomberger, Cheng-Ying Huang, Ashish Agrawal, Willy Rachmady, Anand Murthy
  • Patent number: 11916046
    Abstract: Provided are a display panel and a display device. The display panel includes a display area including pixel areas, each of which includes at least two sub-pixel areas each including a display light-emitting diode. The sub-pixel areas include shared sub-pixel areas, each of which is shared by at least two pixel areas and includes m spare binding areas, where m?2. The shared sub-pixel areas include a first shared sub-pixel area, in which the display light-emitting diode does not emit light. Each first shared sub-pixel area includes n spare light-emitting diodes, where 2?n?m. When the display panel is driven to emit light, standard brightness required to be displayed by each first shared sub-pixel area is L1 and luminous brightness of each spare light-emitting diode in the first shared sub-pixel area is L2, where L2<L1. The present disclosure can weaken influence on display effect caused by shifting of the light-emitting center.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: February 27, 2024
    Assignee: Xiamen Tianma Micro-Electronics Co., Ltd.
    Inventor: Xiao Chi
  • Patent number: 11916179
    Abstract: A printed structure comprises a device comprising device electrical contacts disposed on a common side of the device and a substrate non-native to the device comprising substrate electrical contacts disposed on a surface of the substrate. At least one of the substrate electrical contacts has a rounded shape. The device electrical contacts are in physical and electrical contact with corresponding substrate electrical contacts. The substrate electrical contacts can comprise a polymer core coated with a patterned contact electrical conductor on a surface of the polymer core. A method of making polymer cores comprising patterning a polymer on the substrate and reflowing the patterned polymer to form one or more rounded shapes of the polymer and coating and then patterning the one or more rounded shapes with a conductive material.
    Type: Grant
    Filed: March 24, 2022
    Date of Patent: February 27, 2024
    Assignee: X Display Company Technology Limited
    Inventors: Christopher Andrew Bower, Ronald S. Cok
  • Patent number: 11916051
    Abstract: A display device including a substrate, a plurality of pixels, a plurality of inorganic light-emitting elements, a flattening film, and an inorganic film. The pixels are arrayed on the substrate and display different colors. The inorganic light-emitting elements are provided to the respective pixels. The flattening film surrounds at least a side surface of the inorganic light-emitting element. The inorganic film covers the flattening film and the inorganic light-emitting element. The upper surface of the inorganic light-emitting element is exposed from the flattening film and is in contact with the inorganic film. Alternatively, the flattening film is provided covering the upper surface of the inorganic light-emitting element.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: February 27, 2024
    Assignee: Japan Display Inc.
    Inventors: Yasuhiro Kanaya, Masanobu Ikeda
  • Patent number: 11916048
    Abstract: Reflective bank structures for light emitting devices are described. The reflective bank structure may include a substrate, an insulating layer on the substrate, and an array of bank openings in the insulating layer with each bank opening including a bottom surface and sidewalls. A reflective layer spans sidewalls of each of the bank openings in the insulating layer.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: February 27, 2024
    Assignee: Apple Inc.
    Inventors: Kapil V. Sakariya, Andreas Bibl, Hsin-Hua Hu
  • Patent number: 11908845
    Abstract: A display device includes: a base layer having a first area and a second area extending at least partially around a periphery of the first area; conductive patterns in the second area; an insulating layer over the conductive patterns in the second area; a first electrode and a second electrode on the insulating layer; and a plurality of light emitting elements between the first electrode and the second electrode in the first area and being connected to the first electrode and the second electrode. The first electrode and the second electrode are spaced apart from each other in the first area and are respectively connected to portions of the conductive patterns through contact openings penetrating the insulating layer. The light emitting elements do not overlap the conductive patterns and the insulating layer.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: February 20, 2024
    Assignee: Samsung Display Co., Ltd.
    Inventors: Min Kyu Woo, Kyung Bae Kim, Chong Chul Chai
  • Patent number: 11901343
    Abstract: A semiconductor package having an internal heat distribution layer and methods of forming the semiconductor package are provided. The semiconductor package can include a first semiconductor device, a second semiconductor device, and an external heat distribution layer. The first semiconductor device can comprise a first semiconductor die and an external surface comprising a top surface, a bottom surface, and a side surface joining the bottom surface to the tope surface. The second semiconductor device can comprise a second semiconductor die and can be stacked on the top surface of the first semiconductor device. The external heat distribution layer can cover an external surface of the second semiconductor device and the side surface of the first semiconductor device. The external heat distribution layer further contacts an internal heat distribution layer on a top surface of the first semiconductor die.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: February 13, 2024
    Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.
    Inventors: Bora Baloglu, Ron Huemoeller, Curtis Zwenger
  • Patent number: 11888011
    Abstract: An electronic detection interface comprises a substrate structure and a plurality of detection units in array. The substrate structure includes a circuit film, which comprises a plurality of circuit units in array. The detection units are disposed on a surface of the substrate structure, and are corresponded to the circuit units in a respect manner. Each of the detection units includes at least one resilient conductive pillar, which is electrically connected to each of the circuit units.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: January 30, 2024
    Assignee: ULTRA DISPLAY TECHNOLOGY CORP.
    Inventor: Hsien-Te Chen
  • Patent number: 11864407
    Abstract: A display device includes a substrate having a display area, in which an image is displayed, and a non-display area, in which no image is displayed. The non-display area is disposed on at least one side of the display area. A plurality of pixels is disposed in the display area. An encapsulation layer is disposed on the plurality of pixels. A dam unit is disposed in the non-display area. The dam unit includes a body part and a plurality of protrusions. Each of the plurality of protrusions protrudes from the body part.
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: January 2, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Oh June Kwon, Il Sang Lee, Doo Hwan Kim, Woo Yong Sung, Min Sang Kim, Jin Hwan Jeon, Seung Yong Song
  • Patent number: 11855147
    Abstract: A method for producing a semiconductor component includes: forming a silicon carbide substrate having a body layer formed on a section of a main layer, and a source layer formed on a section of the body layer; forming gate trenches and contact trenches extending through the source layer and the body layer, the gate trenches and contact trenches alternating along a first horizontal direction parallel to a first main surface of the silicon carbide substrate; forming a gate dielectric in the gate trenches; forming a metal structure which includes first sections adjoining the gate dielectric in the gate trenches and second sections in the contact trenches, the second sections adjoining body regions formed from sections of the body layer and source regions formed from sections of the source layer; and removing third sections of the metal structure that connect the first sections to the second sections.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: December 26, 2023
    Assignee: Infineon Technologies AG
    Inventors: Ralf Siemieniec, Wolfgang Bergner
  • Patent number: 11848407
    Abstract: A display device includes a plurality of pixels on a substrate. Each of the pixels includes a first electrode and a second electrode spaced apart from each other on the substrate, and a plurality of light emitting elements, each including a first end portion connected to the first electrode and a second end portion connected to the second electrode. The first electrode includes a plurality of first holes adjacent to the first end portion of each of the light emitting elements.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: December 19, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventors: Gwang Teak Lee, Seong Sik Choi
  • Patent number: 11842947
    Abstract: The fabrication of field-effect transistor (FET) devices is described herein where the FET devices include one or more body contacts implemented between source, gate, drain (S/G/D) assemblies to improve the influence of a voltage applied at the body contact on the S/G/D assemblies. The FET devices can include source fingers and drain fingers interleaved with gate fingers. The source and drain fingers of a first S/G/D assembly can be electrically connected to the source and drain fingers of a second S/G/D assembly. The source fingers and the drain fingers can be arranged in alternating rows.
    Type: Grant
    Filed: May 11, 2021
    Date of Patent: December 12, 2023
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Hailing Wang, Dylan Charles Bartle, Hanching Fuh, David Scott Whitefield, Paul T. DiCarlo
  • Patent number: 11837688
    Abstract: In an embodiment a pixel for a multi-pixel LED module includes a first light-emitting semiconductor chip having a first upper chip side and a first lead-frame section having a first upper side, a first contacting protrusion and a second contacting protrusion, wherein the first contacting protrusion and the second contacting protrusion extend from the first upper side, and wherein the first light-emitting semiconductor chip is embedded in an electrically insulating material such that the first upper side is covered by the electrically insulating material and the first upper chip side and the contacting protrusions are exposed.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: December 5, 2023
    Assignee: OSRAM OLED GmbH
    Inventor: Michael Zitzlsperger
  • Patent number: 11837562
    Abstract: Present disclosure provides a semiconductor structure and a method for fabricating a semiconductor structure. The semiconductor structure includes a substrate, a conductive layer in the substrate, a conductive bump over the substrate and electrically coupled to the conductive layer, and a dielectric stack, including a polymer layer laterally surrounding the conductive bump and including a portion spaced from a nearest outer edge of the conductive bump with a gap, wherein a first thickness of the polymer layer in a first region is greater than a second thickness of the polymer layer in a second region adjacent to the first region, a first bottom surface of the polymer layer in the first region is leveled with a second bottom surface of the polymer layer in the second region, and a dielectric layer underneath the polymer layer.
    Type: Grant
    Filed: April 7, 2021
    Date of Patent: December 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chang-Pin Huang, Tung-Liang Shao, Hsien-Ming Tu, Ching-Jung Yang, Yu-Chia Lai