Abstract: A display device manufacturing method is provided including a display module in which an active area and a non-active area surrounding the active area are defined. A first hole is perforated having a first diameter on the active area. A second hole is formed having a second diameter by irradiating a laser area at least partially surrounding the first hole with a laser. The second diameter is larger than the first diameter.

Abstract: A slicing wafer includes a driver circuit substrate; a plurality of epitaxial layer slices arranged side-by-side on the driver circuit substrate; and a bonding layer, formed between the driver circuit substrate and the plurality of epitaxial layer slices.

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate and a gate structure on the substrate. The semiconductor device includes a channel on the substrate. The semiconductor device includes a source/drain layer on the channel. Moreover, the semiconductor device includes a spacer on a sidewall of the gate structure. The spacer includes a central portion overlapping the channel in a vertical direction, and a protrusion portion protruding from the central portion. Related methods of manufacturing semiconductor devices are also provided.

Abstract: Disclosed in the present specification are an apparatus and a method capable of quickly verifying a plurality of micro LEDs. An LED verification substrate according to the present specification is a micro LED verification substrate having a plurality of verification chips, wherein each verification chip can comprise: a first contact deposited on the upper side of a lower substrate; a first passivation layer deposited on the upper side of the first contact; a second contact deposited on the upper side of the first passivation layer; a second passivation layer deposited on the upper side of the second contact; a first bump electrically connected to the first contact and protruding above the upper surface of the second passivation layer; and a second bump electrically connected to the second contact and protruding above the upper surface of the second passivation layer.

Abstract: The present embodiments provide a transparent electrode having a laminate structure of: a metal oxide layer having an amorphous structure and electroconductivity, and a metal nanowire layer; and further comprising an auxiliary metal wiring. The auxiliary metal wiring covers a part of the metal nanowire layer or of the metal oxide layer, and is connected to the metal nanowire layer.

Abstract: A multi-color LED display comprises pixels, each comprising a first sub-pixel, a second sub-pixel, and a third sub-pixel. The first sub-pixel comprises a first light-emitting diode (LED) that emits a first color of light, the second sub-pixel comprises second LEDs that emit a second color of light different from the first color of light, and the third sub-pixel comprises third LEDs that emit a third color of light different from the first color of light and different from the second color of light. The second LEDs are electrically connected in parallel and the third LEDs are electrically connected in series.

Abstract: A semiconductor device including a fin field effect transistor (fin-FET) includes active fins disposed on a substrate, isolation layers on both sides of the active fins, a gate structure formed to cross the active fins and the isolation layers, source/drain regions on the active fins on sidewalls of the gate structure, a first interlayer insulating layer on the isolation layers in contact with portions of the sidewalls of the gate structure and portions of surfaces of the source/drain regions, an etch stop layer configured to overlap the first interlayer insulating layer, the sidewalls of the gate structure, and the source/drain regions, and contact plugs formed to pass through the etch stop layer to contact the source/drain regions. The source/drain regions have main growth portions in contact with upper surfaces of the active fins.

Abstract: A flexible display apparatus comprises a glass substrate including a flat surface and a glass etching surface that is curved, and a flexible display panel including a bending portion on the glass etching surface.

Abstract: A pair of optical components is used in an isolator that enables electric isolation. Each of the optical components includes: first lens portions arranged on different optical paths and transmitting light in a first direction; second lens portions arranged on different optical paths and transmitting light in the second direction orthogonal to the first direction; and a reflection portion reflecting, in the second direction, the light in the first direction transmitted through the first lens portion and guiding the light to the second lens portion, or reflecting, in the first direction, the light in the second direction transmitted through the second lens portion and guiding the light to the first lens portion The second lens portion included in one of the pair of optical components and the second lens portion included in the other optical component are spaced apart from each other and face each other.

Abstract: A light-emitting element which has low driving voltage and high emission efficiency is provided. The light-emitting element includes, between a pair of electrodes, a hole-transport layer and a light-emitting layer over the hole-transport layer. The light-emitting layer contains a first organic compound having an electron-transport property, a second organic compound having a hole-transport property, and a light-emitting third organic compound converting triplet excitation energy into light emission. A combination of the first organic compound and the second organic compound forms an exciplex. The hole-transport layer contains at least a fourth organic compound whose HOMO level is lower than or equal to that of the second organic compound and a fifth organic compound whose HOMO level is higher than that of the second organic compound.

Abstract: A semiconductor die includes a substrate having a semiconductor surface layer bon a front side with active circuitry including at last one transistor therein and a back side. The sidewall edges of the semiconductor die have at least one damage region pair including an angled damage feature region relative to a surface normal of the semiconductor die that is above a damage region that is more normal to the surface normal of the die as compared to the angled damage feature region.

Abstract: A module-rotation LED dome belongs to the technical field of display screens and includes multiple display devices. Each display device includes 1st-4th light-emitting units. The second light-emitting unit is located beside the first light-emitting unit and oriented with a clockwise rotation of 90 degrees relative to the first light-emitting unit. The third light-emitting unit is located below the second light-emitting unit and oriented with a clockwise rotation of 90 degrees relative to the second light-emitting unit. The fourth light-emitting unit is located beside the third light-emitting unit and oriented with a clockwise rotation of 90 degrees relative to the third light-emitting unit. The 2nd-4th light-emitting units sequentially are rotated clockwise with 90 degrees, so that adjacent full-color LEDs in the 1st-4th light-emitting units cannot form adjacent LEDs of a same color, and there is no condition of appearing a bright blue line.

Abstract: An integrated circuit device having separate dies for programmable logic fabric and circuitry to operate the programmable logic fabric are provided. A first integrated circuit die may include field programmable gate array fabric. A second integrated circuit die may be coupled to the first integrated circuit die. The second integrated circuit die may include fabric support circuitry that operates the field programmable gate array fabric of the first integrated circuit die.

Abstract: Additional “auxiliary” bumps are used to stabilize alignment and reduce slippage of dense arrays of interconnect bumps on opposing die during a bonding process. One example of auxiliary bumps are interdigitated bumps. Interdigitated bumps are more self-aligning and laterally stable because bumps do not meet head-to-head. Rather, the head of a bump on one die falls into the space between bumps on the other die. Another example of auxiliary bumps are nail bumps. In nail bumps, one bump is harder (the nail) and “drives” into the opposing softer bump during bonding. This constrains the lateral movement of the two bumps relative to each other and reduces lateral slippage. In some embodiments, the auxiliary bumps and interconnect bumps are formed in the same process, and also bonded in the same process.

Abstract: A method is provided which includes forming a semiconductor substrate having one or more fins. The method includes forming over the fins a plurality of gate structures. The method includes forming gate spacers on sidewalls of the gate structure. The method includes forming a source/drain region on the semiconductor substrate between each adjacent gate spacer. The method includes depositing an interlevel dielectric layer on the source/drain regions and over the gate structures. The method includes depositing a hardmask on the interlevel dielectric layer. The method includes patterning the hardmask to form a plurality of openings and exposing the top surface of each of the source/drain regions. The method includes depositing an optical planarization layer in a portion of the openings and above the top surface of the gate structures. The method includes etching the interlevel dielectric layer in the opening to form an undercut region below the hardmask.

Abstract: The present invention relates generally to an anodic oxide film for electric contact, to an optoelectronic display, and to a method of manufacturing the optoelectronic display. More particularly, the present invention relates to an anodic oxide film for electric contact to electrically connect an optical element and a substrate in a position therebetween, to an optoelectronic display, and to a method of manufacturing the optoelectronic display.

Abstract: Disclosed is a light-emitting array structure having a substrate, a plurality of light-emitting pixel units, a plurality of first signal wires, a plurality of second signal wires, and an encapsulating layer. The light-emitting pixel units are arranged in array on the substrate. Each light-emitting pixel unit includes a driving chip, a first flat layer, a first redistribution layer, a second flat layer, a second redistribution layer, and a light-emitting diode. Each first signal wire is electrically connected to a corresponding one of the first redistribution layers and extends in a first direction. The second signal wires extend in a level different from the first signal wires. Each second signal wire is electrically connected to a corresponding one of the second redistribution layers and extends in a second direction different from the first direction. The encapsulating layer covers the light-emitting pixel units, the first and second signal wires, and the substrate.

Abstract: A display device includes: a substrate including first areas and second areas alternately arranged in a first direction in a plane view; a first electrode and a second electrode on the substrate and spaced apart from each other in a second direction crossing the first direction; a first insulation layer on the substrate and covering the first electrode and the second electrode; and a light emitting element on the first insulation layer and electrically connected to the first electrode and the second electrode, the first insulation layer having a first thickness in the first area and a second thickness thicker than the first thickness in the second area, and the light emitting element being located in the first area.

Abstract: Some embodiments include a semiconductor construction having a gate extending into a semiconductor base. Conductively-doped source and drain regions are within the base adjacent the gate. A gate dielectric has a first segment between the source region and the gate, a second segment between the drain region and the gate, and a third segment between the first and second segments. At least a portion of the gate dielectric comprises ferroelectric material. In some embodiments the ferroelectric material is within each of the first, second and third segments. In some embodiments, the ferroelectric material is within the first segment or the third segment. In some embodiments, a transistor has a gate, a source region and a drain region; and has a channel region between the source and drain regions. The transistor has a gate dielectric which contains ferroelectric material between the source region and the gate.

Abstract: A display device includes a substrate, an interlayer insulating layer over the substrate, a metal layer over the interlayer insulating layer, and a light emitting element over the metal layer. The interlayer insulating layer includes a plurality of a first depressed portions. The metal layer includes a first region bonding to the light emitting element and a second region surrounding the first region. The second region, a plurality of second depressed portions is provided along the plurality of first depressed portions.