Patents Examined by J. Carroll
  • Patent number: 6342715
    Abstract: A nonvolatile semiconductor memory device comprises a semiconductor substrate, element isolating regions provided in the semiconductor substrate, first element regions, each of which is defined by two adjacent ones of the element isolating regions, and memory cell transistors formed in the element regions, wherein each of the memory cell transistors comprises a first gate insulating film formed on a corresponding one of the element isolating regions, a floating gate electrode formed on the gate insulating film, a second gate insulating film formed on the floating gate electrode, and a control electrode formed on the second gate insulating film and connected in common to a specific number of ones of the memory cell transistors to serve as a word line, and the floating gate includes a first conductive member with side faces in contact with side ends of the two adjacent ones of the element isolating regions and a second conductive member electrically connected to the first conductive member and formed so as to b
    Type: Grant
    Filed: June 15, 1998
    Date of Patent: January 29, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuhiro Shimizu, Seiichi Aritome, Toshiharu Watanabe, Kazuhito Narita
  • Patent number: 6222266
    Abstract: A source electrode, gate electrode, drain electrode, and a gate bus bar connected to said gate electrode are formed on a semiconductor chip. A field effect transistor unit constructed on the semiconductor chip is made up of three adjacent fingers each extending from the source electrode, gate electrode, and drain electrode. The source electrode is formed on the outer edge of the semiconductor chip from the obverse to the reverse surfaces of the semiconductor chip.
    Type: Grant
    Filed: September 2, 1998
    Date of Patent: April 24, 2001
    Assignee: NEC Corporation
    Inventor: Junko Kohno
  • Patent number: 6218722
    Abstract: An improved antifuse which employs the base-emitter junction of a silicided single polysilicon bipolar transistor. The distance between the base metal and emitter metal is shortened and results from self aligning process steps rather than lithographic steps, resulting in a lower and better controlled programming voltage, programming energy and ON state resistance. Typically the conductive filament formed in the new antifuse is about 0.65 microns long and is formed by a voltage pulse having a relatively slow rise time (e.g. 150 microseconds), resulting in improved properties which provide advantages in circuit design and in manufacturing circuits using the new antifuse.
    Type: Grant
    Filed: June 29, 1999
    Date of Patent: April 17, 2001
    Assignee: Gennum Corporation
    Inventors: Andrew V. C. Cervin-Lawry, James D. Kendall, Petrus T. Appelman, Efim Roubakha
  • Patent number: 6215169
    Abstract: In a semiconductor device, the adhesive layer of a tape that is adhered to the surface of a chip is disposed so that there is no overlap with an aperture in the uppermost surface of a semiconductor element. With the usual type of tape, the tape is kept at a distance of at least 0.1 mm from the cover aperture in the surface of the semiconductor element, and in the case in which there are two covers, the tape is kept at a distance of at least 0.1 mm from an aperture at the uppermost surface of the semiconductor element. The aperture includes either a fuse aperture or a bonding bad and fuse aperture.
    Type: Grant
    Filed: May 13, 1999
    Date of Patent: April 10, 2001
    Assignee: NEC Corporation
    Inventor: Michihiko Ichinose
  • Patent number: 6200846
    Abstract: A first silicon film is deposited on a semiconductor substrate. A capacitor dielectric film is deposited on the first silicon film. A second silicon film is deposited on the capacitor dielectric film. The second silicon film is patterned to leave an upper electrode made of the second silicon film above an insulating surface of the semiconductor substrate. A first insulating film is deposited on the upper electrode and the capacitor dielectric film. A lamination structure of the first insulating film and the capacitor dielectric film is anisotropically etched to leave a spacer insulating film made of the first insulating film on the side walls of the upper electrode and to leave a portion of the capacitor dielectric film under the upper electrode and the spacer insulating film. The first silicon film is patterned to leave a lower electrode made of the first silicon film in an area inclusive of the upper electrode and the spacer insulating film.
    Type: Grant
    Filed: December 15, 1998
    Date of Patent: March 13, 2001
    Assignee: Fujitsu Limited
    Inventor: Akiyoshi Watanabe
  • Patent number: 6198135
    Abstract: A semiconductor device having an ESD protection element with an improved ESD resistance is obtainable even if it is formed on the same substrate together with an internal circuit. An SiGe—P well region (3) mainly composed of SiGe having a smaller breakdown field than Si, is formed in the upper portion of a P type Si substrate (1). A drain region (4) and a source region (5) are selectively formed in the surface of the SiGe—P well region (3), and therefore, the boundary between the SiGe—P well region (3) and the drain and source regions (4), (5) defines a PN junction. This results in a MOS transistor for protection comprising the SiGe—P well region (3), the drain region (4), the source region (5), a gate oxide film (6), and a gate polysilicon layer (7).
    Type: Grant
    Filed: June 5, 1998
    Date of Patent: March 6, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Kenichiro Sonoda
  • Patent number: 6198152
    Abstract: A laser trimming link is provided on a field oxide film. An N well is formed below the field oxide film and in the surface of a semiconductor substrate. N well is formed of a retrograde well.
    Type: Grant
    Filed: July 27, 1998
    Date of Patent: March 6, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Hajime Arai
  • Patent number: 6191460
    Abstract: A static random access memory cell is given increased stability and latch-up immunity by using N-type gate NMOS transistors and P-type gate PMOS transistors in the control and sensing circuits, but using the same gate conductivity type for both the NMOS and PMOS memory cell transistors. For example, both NMOS and PMOS memory cell transistors have N-type gates. Weakening the memory cell load transistors by lightly doping the source and/or drain regions further enhances stability.
    Type: Grant
    Filed: September 7, 1999
    Date of Patent: February 20, 2001
    Assignee: Integrated Device Technology, Inc.
    Inventors: Jeong Y. Choi, Chuen-Der Lien
  • Patent number: 6191441
    Abstract: A ferroelectric memory capable of writing data at a small operation voltage has an insulated-gate field effect transistor, a ferroelectric film, and a pair of capacitor electrodes formed on the ferroelectric film and facing each other, one of the pair of capacitor electrodes being electrically connected to the insulated gate. A ferroelectric memory device with a simple structure has an insulated-gate field effect transistor including a source, a drain, and an insulated gate, and a ferroelectric capacitor connected between the drain and the insulated gate.
    Type: Grant
    Filed: October 26, 1998
    Date of Patent: February 20, 2001
    Assignee: Fujitsu Limited
    Inventors: Masaki Aoki, Hirotaka Tamura, Hideki Takauchi, Takashi Eshita
  • Patent number: 6188121
    Abstract: A high voltage capacitor, integratable monolithically on a semiconductor substrate which accommodates a field oxide region overlaid by a first layer of polycrystalline silicon isolated from a second layer of polycrystalline silicon by an interpoly dielectric layer, comprises two elementary capacitors having a first common conductive plate which is formed in the first layer of polycrystalline silicon. Each of these elementary capacitors has a second conductive plate formed in the second layer of polycrystalline silicon above the first plate, and includes said interpoly dielectric layer as an isolation dielectric between the two plates.
    Type: Grant
    Filed: July 20, 1998
    Date of Patent: February 13, 2001
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventors: Livio Baldi, Paolo Ghezzi, Alfonso Maurelli
  • Patent number: 6184559
    Abstract: In a thin-film transistor of multi-gate structure, the width of a channel forming region 108 closest to a drain region 102 is made the narrowest. This prevents a transistor structure closest to the drain region from first deteriorating. Further, the channel length at the vicinity of a center of an active layer is intentionally widened, so that the amount of current flowing through the vicinity of the center of the active layer is decreased and the deteriorating phenomenon due to heat accumulation is prevented. Therefore, a semiconductor device with a high reliability is realized.
    Type: Grant
    Filed: November 14, 1997
    Date of Patent: February 6, 2001
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masahiko Hayakawa, Yosuke Tsukamoto
  • Patent number: 6184103
    Abstract: The present invention provides stable and reliable extremely high resistance polysilicon resistors for use as SRAM load elements, and methods for their fabrication. In an embodiment, a resistor element of a semiconductor device includes at least one polysilicon layer, and a silicon nitride layer deposited directly onto this polysilicon layer. The silicon nitride layer prevents contamination of the polysilicon layer during subsequent fabrication process steps. A method of fabricating a polysilicon resistor on a semiconductor substrate is also provided. The method includes the step of depositing a layer of polysilicon on the substrate, followed by depositing a layer of protective material over the polysilicon layer to form a protected polysilicon layer. After deposition of the protective layer, resistors are formed by implanting dopants into the polysilicon layer, and patterning through lithography, and etching the nitride and the polysilicon layer.
    Type: Grant
    Filed: June 26, 1998
    Date of Patent: February 6, 2001
    Assignees: Sony Corporation, Sony Electronics Inc.
    Inventors: Jia Li, Yaoxiong Wu
  • Patent number: 6180994
    Abstract: An array of sidewall-contacted antifuses is formed by a method that reduces the sensitivity of the array to masking alignment errors. The array includes a plurality of spaced-apart bit lines which are formed in a semiconductor material. Rows and columns of insulated contacts are formed on the semiconductor material such that each bit line is contacted a plurality of times by an insulated contact. In each row of contacts, each contact has an exposed sidewall. A plurality of word lines are formed over the contacts such that a word line is formed over each exposed sidewall in a row of exposed sidewalls. The word line includes a dielectric layer and a conductive layer.
    Type: Grant
    Filed: January 19, 1999
    Date of Patent: January 30, 2001
    Assignee: National Semiconductor Corporation
    Inventors: Albert Bergemont, Alexander Kalnitsky
  • Patent number: 6180978
    Abstract: A counter-doped epitaxial silicon (doped opposite to the substrate type) is used to form the buried layer in a CMOS transistor, while maintaining an abrupt channel profile. Shallow source/drain junctions with abrupt source/drain profiles may be formed using raised (or elevated) source/drain design. The invention encompasses a transistor structure including a doped silicon substrate, and an oppositely-doped epitaxial silicon layer formed on the substrate. A gate is formed on the epitaxial layer, the gate defining a channel region in the epitaxial layer underneath the gate. A layer is formed on the epitaxial silicon layer on opposing sides of, and is electrically isolated from, the gate.
    Type: Grant
    Filed: December 18, 1998
    Date of Patent: January 30, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Amitava Chatterjee, Richard A. Chapman, Syed Suhail Murtaza
  • Patent number: 6180992
    Abstract: A fuse configuration for a semiconductor storage device has a multiplicity of fuses on a semiconductor body. The fuses are disposed in two or more planes so as to save chip area. The fuses are programmed individually by melting and thus breaking certain conducting connections. The fuses may be fused by crossing two laser beams and melting the fuse at which the beams cross.
    Type: Grant
    Filed: August 28, 1998
    Date of Patent: January 30, 2001
    Assignee: Infineon Technologies AG
    Inventors: Holger Göbel, Gunnar Krause
  • Patent number: 6180996
    Abstract: An aluminum wire is connected to a P-type layer of a polydiode element through a resistive element consisting of a barrier metal film and a tungsten plug. Another aluminum wire is connected to an N-type layer of the polydiode element through another resistive element consisting of another barrier metal film and another tungsten plug. Thus, a semiconductor device including a polydiode element which is resistant to surge or contamination is provided.
    Type: Grant
    Filed: July 15, 1998
    Date of Patent: January 30, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hiroshi Onoda, Masaaki Mihara, Hiroshi Takada
  • Patent number: 6177714
    Abstract: In a laser beam make-link programmable semiconductor device, a pair of conductor strips are formed in the same level plane on a lower level insulator film formed on a semiconductor substrate, and are separated from each other in such a manner that opposing ends of the pair of conductor strips are separated by a predetermined distance smaller than a film thickness of the upper level insulator film. An upper level insulator film substantially transparent to a laser beam, is formed on the conductor strips. With this arrangement, even if a trimming laser beam has a small energy, the laser beam permeates through the upper level insulator film to reach and melt the opposing ends of the pair of conductor strips, with the result that the opposing ends of the pair of conductor strips are short-circuited.
    Type: Grant
    Filed: February 13, 1998
    Date of Patent: January 23, 2001
    Assignee: NEC Corporation
    Inventor: Nobutaka Nagai
  • Patent number: 6175145
    Abstract: The present invention provides a fuse of a semiconductor device and a method of forming a fuse of a semiconductor device. The method of the invention includes forming an underlying metal conductor on a semiconductor substrate, forming an insulating film over the underlying metal conductor, and selectively etching regions of the insulating film. One of the regions of the insulating film is etched to form a via contact region exposing the underlying metal conductor. A second region is etched to form a groove in the insulating film for the fuse metal. Metal is buried within the second etched region of the insulating film and the via contact region to respectively form a fuse metal pattern and a via contact metal layer. The fuse metal pattern can be formed from copper and/or tungsten.
    Type: Grant
    Filed: September 30, 1998
    Date of Patent: January 16, 2001
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Hun Lee, Jong-Hyon Ahn
  • Patent number: 6172388
    Abstract: An improved method for fabricating DRAM with a thin film transistor can increase reading and writing speed. In this method, a substrate with a transfer transistor, a word line, a bit line and an interlayer dielectric layer is provided. A bit line contact and a terminal contact are formed in the interlayer dielectric layer. The bit line contact couples to the bit line and the terminal contact couples to the transfer transistor. The terminal contact is a T-shaped structure. An oxide layer is formed to cover the interlayer dielectric layer and the terminal contact to expose the bit line contact. A polysilicon layer is formed to cover the oxide layer and the bit line contact. An ion implantation step is performed to form a first doped region and a second doped region in the polysilicon layer. The polysilicon layer is patterned to make the first doped region into a source region and to make the second doped region into a drain region.
    Type: Grant
    Filed: March 16, 1999
    Date of Patent: January 9, 2001
    Assignee: United Semiconductor Corp.
    Inventor: Shu-Ya Chuang
  • Patent number: 6172402
    Abstract: An integrated circuit includes a plurality of transistors formed to include insulative punchthrough regions. Each of the plurality of transistors includes a channel formed upon a substrate, an insulative punchthrough region formed below the channel, a source formed upon the insulative punchthrough region residing adjacent a first end of the channel, a drain formed upon the insulative punchthrough region residing adjacent a second end of the channel, a gate oxide formed above the channel and a gate conductor formed above the gate oxide. Isolation regions may also be formed in the substrate that have an etch stop defination that was formed upon formation of the insulative punchthrough region. A voltage threshold region may be formed between the gate oxide and the channel and lightly doped regions may be formed adjacent the channel. The insulative punchthrough region may be and oxide layer formed within the substrate in an oxygen implant step that also formed the etch stop defination.
    Type: Grant
    Filed: June 4, 1998
    Date of Patent: January 9, 2001
    Assignee: Advanced Micro Devices
    Inventors: Mark I. Gardner, Mark C. Gilmer, Daniel Kadosh