Abstract: A semiconductor structure having multiple thicknesses of high-k gate dielectrics and a process of manufacture. In one embodiment, semiconductor structure is provided that includes a substrate, and a high permittivity layer is disposed on the substrate, the high permittivity layer having two or more areas with different thicknesses. A plurality of gate electrodes are disposed in the two or more areas on the high permittivity layer. In another embodiment, a process for constructing a semiconductor structure includes depositing a high permittivity layer on the substrate, the high permittivity layer having a first thickness. A first set of one or more gate electrodes are formed on the high permittivity layer having the first thickness. Selected portions of the high permittivity layer are then removed, whereby the high permittivity layer is reduced to a second thickness. Then a second set of gate electrodes are formed on the selected portions of the high permittivity layer having the second thickness.

Abstract: A nitride light emitting diode is fabricated on a transparent sapphire substrate. The LED is then mounted upside-down on a conductive silicon substrate with a bottom electrode to serve as the output terminal for the cathode of the LED. The LED die is partially etched to expose the anode of the LED, where a top electrode is formed. In comparison with conventional LED structure with both electrodes located on top of the die, moving one electrode to the bottom allows more light to be transmitted upward and reflects the light incident downward. For equal amount of light emission, the new structure occupies less area.

Abstract: A semiconductor device which has a MOS transistor having a gate electrode composed of a first conductive film formed on a silicon substrate; a resistance element composed of a second conductive film formed on a field insulating film formed on the silicon substrate; and a plurality of conductive film patterns formed in parallel at predetermined intervals on the surface of the field insulating film, wherein the plurality of conductive film patterns are of the first conductive film type connected with a predetermined potential, and the top surface and side of each of the plurality of conductive film patterns are covered with an insulating film; wherein the resistance element is formed reciprocative-crossing several times in the orthogonal direction to the plurality of conductive film patterns through the insulating film on the plurality of conductive film patterns.

Abstract: The contamination introduced into a conventional fuse via the window opening of the fuse is eliminated by forming a fuse with a cavity. When the fuse is programmed by passing a current through the fuse which is sufficient to heat up the fuse material, the heated fuse material flows up into the cavity, thereby providing an open current path.

Abstract: A semiconductor device (10) is formed to have multiple external connection pads (17, 18) for an active element (12). The multiple external connection pads (17, 18) are electrically connected together with a electrical link (19). After testing, the electrical link (19) is removed to disconnect the multiple external connection pads (17, 18) from each other.

Abstract: In order to solve the above-described problem, a semiconductor integrated circuit according to the present invention comprises a semiconductor chip, a core area formed over the semiconductor chip and comprised of predetermined circuits, and a plurality of input/output unit cells placed along peripheral edge portions of the semiconductor chip so as to surround the core area and shaped in the form of bent patterns. Further, a semiconductor integrated circuit according to another invention comprises a semiconductor chip, a core area formed over the semiconductor chip and comprised of predetermined circuits, and a plurality of input/output unit cells placed aslant toward peripheral portions of the semiconductor chip so as to surround the core area.

Abstract: A ferroelectric capacitor and a method of manufacturing the same are provided for reducing a crystal grain size while maintaining excellent ferroelectric properties so as to achieve a reduction in device size. A lower electrode, a ferroelectric layer and an upper electrode are formed on a substrate. The ferroelectric layer is formed into a plurality of stacked layers including an oxide of a layered crystal structure (Bi.sub.x (Sr, Ca, Ba).sub.y (Ta, Nb).sub.2 O.sub.9 .+-..sub.d). Proportion `y` of (Sr, Ca, Ba) in at least one of the layers is different from those of the other layers. That is, a variation in proportion `y` of (Sr, Ca, Ba) is provided in the ferroelectric layer. As a result, excellent ferroelectric properties are obtained and the crystal grain size of the oxide is reduced.

Abstract: An electrode structure for use in a chalcogenide memory is disclosed. The electrode has a substantially frusto-conical shape, and is preferably formed by undercut etching a polysilicon layer beneath an oxide pattern. With this structure, improved current densities through the chalcogenide material can be achieved.

Abstract: The preferred embodiment of the present invention provides a method for defining three regions on a semiconductor substrate using a single masking step. The preferred embodiment uses a photoresist material having, simultaneously, both a positive tone and a negative tone response to exposure. This combination of materials can provide a new type of resist, which we call a hybrid resist. The hybrid resist comprises a positive tone component which acts at a first actinic energy level and a negative tone component which acts at a second actinic energy level, with the first and second actinic energy levels being separated by an intermediate range of actinic energy. When hybrid resist is exposed to actinic energy, areas of the resist which are subject to a full exposure cross link to form a negative tone line pattern, areas which are unexposed form remain photoactive and form a positive tone pattern, and areas which are exposed to intermediate amounts of radiation become soluble and wash away during development.

Abstract: A vertically integrated semiconductor component is provided with component levels disposed on different substrates. The substrates are joined by a connecting layer of benzocyclobutene and an electrical connection is provided between component levels by a vertical contact structure. A low-stress gluing is provided by the benzocyclobutene connecting layer.

Abstract: The present invention is described in several embodiments depicting structures and methods to form these structures. A first embodiment is a structure having a silicon dioxide film bonded to a metal film comprising: a metal nitride film bonded to the metal film; and the silicon dioxide film bonded to the metal nitride film. A second embodiment is a structure having a silicon dioxide film bonded to a metal film comprising: a metal oxide film bonded to the metal film; and the silicon dioxide film bonded to the metal oxide film. A third embodiment is a structure having a silicon dioxide film bonded to a metal film comprising: a metal/oxide/nitride film bonded to the metal film; and the silicon dioxide film bonded to the metal/oxide/nitride film.

Abstract: A semiconductor device (10) is formed to have multiple external connection pads (17, 18) for an active element (12). The multiple external connection pads (17, 18) are electrically connected together with a electrical link (19). After testing, the electrical link (19) is removed to disconnect the multiple external connection pads (17, 18) from each other.

Abstract: A semiconductor memory device includes a floating gate, a control gate, source and drain regions, a lightly doped region of the second conductivity type, and a silicide layer. The floating gate is formed on a semiconductor substrate of the first conductivity type via a gate insulating film. The control gate is formed on the floating gate via an insulating film. The source and drain regions are formed by diffusing an impurity of the second conductivity type in the surface of the semiconductor substrate on the two sides of the floating gate. The lightly doped region is formed with a surface exposed at a position distant from the floating gate in at least the source region. The lightly doped region has an impurity dose lower than that of the source region. The silicide layer is formed on the exposed surface of the lightly doped region.

Abstract: The present invention, in one embodiment provides for use in a semiconductor device having a metal or dielectric layer located over a substrate material, a method of forming an anti-reflective layer on the metal layer and a semiconductor device produced by that method. The method comprises the steps of forming a dielectric layer, such as an amorphous silicon, of a predetermined thickness on the metal layer or dielectric and forming a gradient of refractive indices through at least a portion of the predetermined thickness of the dielectric layer by an oxidation process to transform the dielectric layer into an anti-reflective layer having a radiation absorption region and a radiation transmission region. In advantageous embodiments, the dielectric layer may be a substantially amorphous, non-stacked silicon layer. Additionally, the thickness of the dielectric layer may range from about 4.5 nm to about 150 nm.

Abstract: A thin film transistor matrix device comprises an insulating substrate, a plurality of picture element electrodes arranged in a matrix on the insulating substrate, source electrodes connected to the respective picture element electrodes, drain electrodes opposed to the respective source electrodes, operational semiconductor layers sandwiched by the source electrodes and the drain electrodes, and gate electrodes formed on the operational semiconductor layers through gate insulating films, each gate electrode being narrowed with respect to the associated gate insulating film so that side walls of the gate electrode forms a step with respect to side walls of the associated gate insulating film which is a substrate of the gate electrode.

Abstract: A microelectronic capacitor is formed by forming a first tantalum pentoxide film on a conductive electrode and annealing the first tantalum pentoxide film in the presence of ultraviolet radiation and ozone. The forming step and annealing step are then repeated at least once to form at least a second tantalum pentoxide film which has been annealed in the presence of ultraviolet radiation, on the first tantalum pentoxide film. A second conductive electrode may then be formed on the tantalum pentoxide layer. The resultant tantalum pentoxide layer can have a thickness which exceeds 45 .ANG., yet has a reduced leakage current by filling the oxygen vacancies across the thickness thereof.

Abstract: The present invention relates to a high performance, high reliability antifuse using conductive electrodes. The problem of switch-off of the programmed antifuses is solved by reducing the thermal conductivity of the conductive electrodes. This is achieved by using lower thermal conductivity conductors for the electrodes or by using thinner electrodes to increase thermal resistance. According to a first aspect of the present invention, the problem of switch-off in conductor-to-conductor antifuses is solved by utilizing conductive electrode materials having a relatively lower thermal conductivity than prior art electrode materials. According to a second aspect of the present invention, the problem of switch-off in conductor-to-conductor antifuses is solved by utilizing relatively thin electrodes, thus increasing their thermal resistance.

Abstract: A static self-locking micro-circuit-breaker includes a first MOS depletion transistor of a first type connected by its drain to a first main terminal and by its gate to a second main terminal, a second MOS depletion transistor of second type connected by its drain to the second main terminal and by its source to the source of the first transistor, a third MOS depletion transistor of the first type connected by its drain to the first main terminal, by its gate to the second main terminal, and by its source to the gate of the second transistor.

Abstract: The present invention relates to a method for, in the manufacturing of an integrated circuit, producing a capacitor with metallic conducting electrodes and to the capacitor itself and to the integrated circuit, which preferably are intended for high-frequency applications. According to the invention, a lower electrode (17,63,67) is produced through depositing a first metal layer (15) onto a layer structure (11) comprising lowermost a substrate and uppermost an insulating layer (13). An insulating layer (19) is deposited over the first metal layer (15), whereafter an electrical connection (25) to the lower electrode (17,63,67) is produced by etching a via hole (21) through said insulating layer (19), which via hole (21) is plugged. There-after the first metal layer (15) is uncovered within a predetermined area (33), whereafter a dielectric layer (35) is deposited, patterned and etched in such a way that it overlaps (39) said predetermined area (33).

Abstract: A ferroelectric layer having a low dielectric constant which is used for a ferroelectric memory element is provided. Also, the ferroelectric layer having a high melting point used for the ferroelectric memory element is provided. An FET 20 has a stacked structure including a gate oxidation layer 24, a floating gate 26, a ferroelectric layer 28, and a control gate 30 deposited on a channel region CH in that order, the channel region CH being formed in a semiconductor substrate 22 made of silicon. The ferroelectric layer 28 consists of a thin film made of a mixed crystal composed of Sr.sub.2 (Ta.sub.1-x Nb.sub.x).sub.2 O.sub.7. The crystal structure of both Sr.sub.2 Nb.sub.2 O.sub.7 and Sr.sub.2 Ta.sub.2 O.sub.7 is pyramid quadratic structure, and their lattice constants are similar to each other. Their relative dielectric constants are low, and their melting points are high. Curie temperature related with their ferroelectricity is, however, too high in Sr.sub.2 Nb.sub.2 O.sub.7 and too low in Sr.sub.2 Ta.sub.