Abstract: A variable delay circuit has plural delay stages connected in series for providing delay time during signal propagation therethrough, and a high resistive delay signal line on a lower level of a multi-layered semiconductor structure and a low resistive breakable signal line on an upper level of the multi-layered semiconductor structure are connected in parallel between two nodes of each delay stage so as to change the total resistance of the delay stage; when a manufacturer decreases the delay time, the low resistive breakable signal line is broken, and the signal is propagated through the high resistive signal line instead of the low resistive breakable signal line.

Abstract: A semiconductor device capacitor structure comprises a semiconductor substrate having an impurity diffusion region; an insulating layer formed on the semiconductor substrate and having a contact hole on the impurity diffusion region; a first lower electrode of a half ring type formed on the insulating film along an upper edge of the contact hole; a second lower electrode formed on a surface of the substrate exposed through the contact hole, a wall of the contact hole, and the first lower electrode; a dielectric layer formed on the first and second lower electrodes; and an upper electrode formed on the dielectric layer. This structure increases capacitance, thereby improving the characteristics and reliability of the device.

Abstract: A method and structure for customizing or repairing integrated circuits using passivated tungsten fuses and low-power energy beams to select which tungsten fuses are to be removed. The tungsten fuses are formed in an array to connect possible connection points of the device. A low-power energy source then selects undesired connection points, and a conventional etch removes the selected tungsten fuses, thereby customizing or repairing the integrated circuit. Because neither precision custom masks nor high energy laser sources are required, the problems associated with conventional methods are reduced or eliminated.

Abstract: A monolithic assembly includes vertical power semiconductor components formed throughout the thickness of a low doped semiconductive wafer of a first conductivity type, whose bottom surface is uniformly coated with a metallization. At least some of these components, so-called autonomous components, are formed in insulated sections of the substrate, whose lateral insulation is provided by a diffused wall of the second conductivity type and whose bottom is insulated through a dielectric layer interposed between the bottom surface of the substrate and the metallization.

Abstract: A semiconductor device comprises a semiconductor substrate, a source/drain region formed in the substrate, a gate oxide layer on the substrate between the source/drain region, a conductive layer on the gate oxide layer, a spacer around a side wall of the gate, and an air gap between the gate and the spacer. The spacer is not directly connected with the gate. The air gap is formed between the gate and the spacer.

Abstract: An integrated digital circuit is protected from reverse engineering by fabricating all transistors of like conductivity with a common size and geometric layout, providing a common layout for different logic cells, connecting doped circuit elements of like conductivity with electrically conductive doped implants in the substrate rather than metalized interconnections, and providing non-functional apparent interconnections that are interrupted by non-discernable channel stops so that all cells falsely appear to have a common interconnection scheme. The camouflage is enhanced by providing a uniform pattern of metal leads over the transistor array, with a uniform pattern of heavily doped implant taps from the transistors for connection to the leads; undesired tap-lead connections are blocked by channel stops.

Abstract: A semiconductor device with first and second types of devices formed in a semiconductor substrate with a barrier layer formed over the surface of the semiconductor device including over the first and second types of devices with the barrier layer removed from over the first type of device. The first type of device is a positive charge sensitive device such as a nonvolatile memory device. The semiconductor device has a hydrogen getter layer formed under the barrier layer.

Abstract: A method of fabricating a tungsten contact in a semiconductor device comprises providing an oxide layer on a region of a silicon substrate; depositing a sealing dielectric layer over the oxide layer; and depositing an interlevel dielectric layer over the sealing layer. The interlevel dielectric layer, the sealing dielectric layer and the oxide layer are then etched through as far as the substrate thereby to form a contact hole and to expose the said region. A dopant is implanted into the said region whereby the implanted dopant is self-aligned to the contact hole. The substrate is thermally annealed. Tungsten is selectively deposited in the contact hole and an interconnect layer is deposited over the deposited tungsten contact. The invention also provides a semiconductor device which incorporates a tungsten contact and which can be fabricated by the method.

Abstract: The present antifuse includes a base having a first electrode thereon which defines a top surface and a side surface. Antifuse material is disposed on the first electrode on at least a portion of the top surface and at least a portion of the side surface, with a second electrode on the antifuse material. Due to this configuration, defect problems in etching oxide as part of the antifuse structure are avoided, and meanwhile capacitance of the device is very low.

Abstract: A three-dimensional, deep-trench, high-density ROM and its manufacturing method are provided. The ROM device comprises a silicon substrate having a plurality of parallel trenches above it surface, wherein, between every two adjacent trenches, there is a higher region. During programming of the ROM device, deeper trenches are formed to define the OFF-state non-conducting memory cells, so that misalignment problems that lead to transistor cell leakage are prevented. The ROM device provides reduced breakdown of the source/drain regions as well.

Abstract: Providing a power control device of a simple structure which increases the reliability of a circuit as incorporated therein. A semiconductor component constituting a power control device comprises a semiconductor chip, atop of which a cathode and a gate are formed via an oxide film portion. The cathode comprises a pad portion, a fusion portion and a contact portion. The pad portion and the contact portion are interconnected by the fusion portion only. An anode is formed at the bottom of the semiconductor chip. With the flow of a fusing current through the fusion portion, the fusion portion is fused by heat generated therefrom whereby the current flow through the cathode and the anode is interrupted.

Abstract: A method of forming a guard wall for a semiconductor die is described. A dielectric layer is deposited over a semiconductor substrate. The dielectric layer is patterned to form a guard wall opening extending through the dielectric layer. The guard wall opening lies adjacent to an electrically active region of the die. The guard wall opening has a pattern without any straight line segments greater than about 10 .mu.m long. A first layer is deposited over the substrate and etched to form a first layer sidewall spacer along a side of the guard wall opening. A second layer is deposited within the guard wall opening to form the guard wall.

Abstract: Integrated circuitry fuse forming methods, integrated circuitry programming methods, and related integrated circuitry are described. In one implementation, a first layer comprising a first conductive material is formed over a substrate. A second layer comprising a second conductive material different from the first conductive material is formed over the first layer and in conductive connection therewith. A fuse area is formed by removing at least a portion of one of the first and second layers. In a preferred aspect, an assembly of layers comprising one layer disposed intermediate two conductive layers is provided. At least a portion of the one layer is removed from between the two layers to provide a void therebetween. In another aspect, programming circuitry is provided over a substrate upon which the assembly of layers is provided.

Abstract: A MOS capacitor has a p-type silicon substrate, an n-type impurity diffusion area formed by implanting an impurity into a region of the silicon substrate, a silicon oxide layer formed on the diffusion area, and a polysilicon electrode formed on the silicon oxide layer. An impurity profile is formed in the region such that the concentration of the impurity increases from a surface common to the diffusion area and the silicon oxide layer towards the inside of the silicon substrate. The concentration of the impurity at the interface is less than or equal to 1.times.10.sup.20 cm.sup.-3, and a peak concentration lies at a depth of more than 0.05 .mu.m under the interface. This controls accelerated oxidization during the thermal oxidization and also controls the dependence of the capacitance on the voltage.

Abstract: A method for producing a semiconductor device which comprises a step for forming a gate electrode on a main surface of a semiconductor substrate via a gate oxide film, and a step for directing plasma ions with a gas mixture comprising a first gas containing a hydride of an impurity element and a second gas containing a fluoride of the impurity element into a surface of the semiconductor substrate.

Abstract: A power semiconductor component having a cell structure includes a metallic resistance track that is insulated from the semiconductor body of the power semiconductor component and from a control electrode by a non-conductive layer. The resistance track is provided in a lateral region between cells of the power semiconductor. The active area of the component is not made smaller by the presence of the resistance track and the resistance track is produced simultaneously with a metallic layer of the component which provides electrical contact with a main electrode of the power semiconductor so that no additional manufacturing steps are required for adding the resistive track.

Abstract: The device has an SCR structure in a P surface zone of a silicon die. A P+ anode region for connection to an I/O terminal to be protected is formed in an N region, as well as an N+ contact region; an N+ cathode region is formed in another N region for connection to the earth of the integrated circuit. The striking potential of the SCR, that is, the intervention potential of the protection device, is determined by the reverse breakdown of the junction between the first N region and the P-body surface zone. This potential is influenced by an electrode which is disposed over the junction and is connected to the cathode constituting the gate of a cut-off N-channel MOS transistor. The concentrations are selected in a manner such that the P-channel MOS transistor defined by the P region, by the portion of the first region over which the electrode is disposed, and by the P-body, has a conduction threshold greater than the striking potential.

Abstract: Two types of programmable elements, fuses and antifuses, are disclosed for interconnecting the terminals of electronic components mounted on printed circuit boards (PCBs), multichip modules (MCMs) or in integrated circuit packages (IC packages). Both types of programmable elements can be fabricated as part of the regular processes used to fabricate PCBs, MCMs, or IC package (pin grid array). For fuses and antifuses, the material, geometry and dimensions can be varied to minimize the real estate and maximize programming efficiency (reduce programming time). Each type of programmable element, fuse or antifuse, can be separately used in matrices to form programmable board and package substrates. When both types of programmable elements are used together, more efficient placement and route architectures take advantage of the characteristics of each type of programmable element. Furthermore, combinations of both fuses and antifuses in the same structure allows the architecture to be reprogrammable.

Abstract: A semiconductor device, which can realize a high speed operation of a transistor with a small leakage current whenever such operation is required, is disclosed. A SOI layer is formed on a monocrystalline silicon substrate through a silicon oxide film, and C-MOS circuits (inverter circuits) are configured with P-channel type MOSFETs and N-channel type MOSFETs on the layer. A bias electrode for P-channel is disposed within the silicon oxide film facing the P-channel type MOSFETs, while a bias electrode for N-channel is disposed within the silicon oxide film facing the N-channel type MOSFETs.

Abstract: An antifuse based PROM cell design allows large currents to be sinked during cell programming to ensure low programmed resistance of the cell while using minimum-geometry select devices. This is achieved by utilizing a pseudo SCR latchup effect during programming. The regions in the semiconductor substrate forming lower antifuse electrodes for the antifuses in the PROM cells are doped at low levels with phosphorus. An antifuse layer formed from an oxide, oxide-nitride, or oxide-nitride-oxide antifuse layer, is formed over the lower antifuse electrode, and an upper antifuse electrode is formed from polysilicon. A minimum-geometry N-Channel select transistor is formed in series with the antifuse to complete the PROM cell. The drain and source diffusions of the select transistor are arsenic doped and the drain diffusion is contiguous with the lower antifuse electrode. A bit line is contacted to the upper antifuse electrode and the select transistor gate is part of a polysilicon word line.