Abstract: A method of volume compressed header identification includes reading, by a processing device of a host, compressible data on a sector of a storage volume of a storage array. The method further includes compressing the compressible data to generate compressed data for the sector. The method further includes adding, by the processing device of the host, metadata associated with the storage volume to the compressed data. The method further includes writing the compressed data, including the added metadata, to the sector of the storage volume of the storage array.

Abstract: Adjusting storage capacity in a computing system that includes a computing device configured to send access requests to a storage device characterized by a first storage capacity, including: reducing data; determining, in dependence upon an amount of storage capacity saved by reducing the data, an updated storage capacity for the storage device; and exporting an updated storage capacity to the computing device.

Abstract: An electronic control device includes a nonvolatile memory having allocated two storage areas that are exclusively switchable between an active state and an inactive state, the two storage areas being set such that in a state in which a program is written in the storage area in the active state, a program is written for updating to the storage area in the inactive state in response to an instruction from an external device, followed by switching the storage area in the active state to the inactive state and switching the storage area in the inactive state to the active state. In the electronic control device, when the program written in the storage area in the active state differs from the program written in the storage area in the inactive state, the program written in the storage area switched to the active state is copied to the storage area in the inactive state.

Abstract: Various embodiments include methods and devices for implementing a criterion aware cache replacement policy by a computing device. Embodiments may include updating a staling counter, writing a value of a local counter to a system cache in association with a location in the system cache for with data, in which the value of the local counter includes a value of the staling counter when (i.e., at the time) the associated data is written to the system cache, and using the value of the local counter of the associated data to determine whether the associated data is stale.

Abstract: Techniques for extending a storage system having a first pool involve adding, in response to a request, second storage devices, wherein the first pool is generated using first storage devices and based on a first standard. The first pool includes first stripes created using the first standard, and the number of the second storage devices equals a first stripe width associated with the first standard. Such techniques further involve creating a second pool using the second storage devices and based on a second standard, wherein a second stripe width associated with the second standard equals the first stripe width. Such techniques further involve creating second stripes in the second pool using the second storage devices and based on the second standard. Such techniques further involve storing data of at least one of the first stripes to a corresponding stripe of the second stripes according to a data shuffle rule.

Abstract: For a non-volatile memory that uses hard bit and soft bit data in error correction operations, to reduce the amount of soft bit data that needs to be transferred from a memory to the controller and improve memory system performance, the soft bit data can be compressed before transfer. After the soft bit data is read and stored into the internal data latches associated with the sense amplifiers, it is compressed within these internal data latches. The compressed soft bit data can then be transferred to the transfer data latches of a cache buffer, where the compressed soft bit data can be consolidated and transferred out over an input-output interface. Within the input-output interface, the compressed data can be reshuffled to put into logical user data order if needed.

Abstract: Some embodiments provide a method for performing data message processing at a smart NIC of a computer that executes a software forwarding element (SFE). The method stores (i) a set of cache entries that the smart NIC uses to process a set of received data messages without providing the data messages to the SFE and (ii) rule updates used by the smart NIC to validate the cache entries. After a period of time, the method determines that the rule updates are incorporated into a data message processing structure of the SFE. Upon incorporating the rule updates, the method deletes from the smart NIC (i) the rule updates and (ii) at least a subset of the cache entries.

Abstract: One or more data items is received by a processing device managing one or more memory devices partitioned into a plurality of die partitions. The one or more data items is determined to be written sequentially to one or more blocks within a die partition of the plurality of die partitions. Metadata associated with the one or more data items is written sequentially to one or more blocks across the plurality of die partitions.

Abstract: Methods, systems, and devices for suspension during a multi-plane write procedure are described. A memory system may perform a multi-plane write procedure by writing to a set of planes in parallel. Upon detecting a defective plane in the set of planes, the memory system may suspend writing to the defective plane until writing to the other planes in the set of planes is finished. The memory system may then resume writing to the defective plane.

Abstract: According to one embodiment, an I/O command control apparatus receives authorization information. The authorization information indicates whether or not to permit an execution of an I/O command. The apparatus verifies whether the received authorization information is not tampered with, and whether the received authorization information is issued from a known authorization server. In a case where the authorization information is not tampered with, and is issued from the known server, the apparatus verifies whether or not the authorization information permits to execution of the I/O command. The apparatus permits or prohibits the execution of the I/O command or execution of a control command generated from the I/O command, based on the authorization result.

Abstract: A memory system includes a main memory, an auxiliary memory, a redundancy circuit, an extension control terminal, and a multiplexer. The main memory has a line width, and includes a write data input. The auxiliary memory has the same line width as the main memory, and includes a write data input. The redundancy circuit includes and input and an output. The input is coupled to the write data input of the main memory. The multiplexer includes a first input, a second input, a control input, and an output. The first input is coupled to the write data input of the main memory. The second input is coupled to the output of the redundancy circuit. The control input is coupled to the extension control terminal. The output of the multiplexer is coupled to the write data input of the auxiliary memory.

Abstract: A method of managing data during execution of an application for use in a system that includes a host memory, a near memory, and a near device associated with the near memory. The application uses a working set of data that is distributed between the far memory and the near memory. The method includes counting a number of times that the near device accesses a unit of the working set of data from the far memory, determining whether the number of times exceeds a dynamically changing access counter threshold, wherein the dynamically changing access counter threshold is calculated dynamically based on a static threshold that is set for the system, and responsive to determining that the number of times exceeds the dynamically changing access counter threshold, migrating the unit of data from the far memory to the near memory.

Abstract: A storage system has NVRAM (non-volatile random-access memory), solid-state storage memory, and a processor to perform a method. The method includes allocating virtual units of NVRAM with mapping of the virtual units to physical memory. The method includes writing data having various sizes into allocated first virtual units of memory and into allocated second virtual units of memory. The first virtual units of memory each include a first contiguous physical addressed amount of NVRAM having a first size. The second virtual units of memory each include an amount of NVRAM having a second size. The method includes relocating at least some of the data such that a portion of the allocated second virtual units of memory become available for the allocating.

Abstract: Methods, systems, and devices for command prioritization techniques for reducing latency in a memory system are described. In some examples, a host system may receive a set of commands from one or more virtual machines to access a common memory system. The host system may store the set of command in a command queue associated with the memory system and arrange the set of command according to order that is based on one or more identified pattern of accessing sequential addresses in the set of commands. The host system may transmit the set of command to the memory system based on the order and the memory system may execute the commands according to the order.

Abstract: Embodiments provide a read operation circuit, a semiconductor memory, and a read operation method. The read operation circuit includes: a data determination module configured to read read data from the memory bank, and determine, according to the number of bits of a data change between previous read data and current read data, whether to invert the current read data to output global bus data for transmission through a global bus and inversion flag data for transmission through an inversion flag signal line; a data receiving module configured to determine whether to invert the global bus data according to the inversion flag data to output cache data; a parallel-to-serial conversion circuit configured to perform parallel-to-serial conversion on the cache data to generate output data of a DQ port; and a data buffer module configured to determine an initial state of the global bus according to enable signal and current read data.

Abstract: A data processing system and method for accessing a heterogeneous memory system including a processing unit are provided. The heterogeneous memory system includes a memory module and high bandwidth memory (HBM) including a processing-in-memory (PIM) circuit combined with a memory controller. The memory controller is configured to detect a data array required for an arithmetic operation from a memory module or the HBM by using a border index value when the arithmetic operation is performed by the PIM circuit of the HBM and generate a memory module command set and an HBM command set using physical address spaces respectively designated in the memory module and the HBM.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller communicates with a host. The host includes a host memory and a circuit. The circuit accesses the host memory in a unit of first size. When an address designated as a first location of the host memory where data read from the nonvolatile memory is to be stored is not aligned with a boundary in the host memory defined in a unit of the first size, the controller transmits a first packet which has a size from the first location to the boundary and includes the read data to be stored from the first location, and transmits a second packet which has the first size and includes the read data to be stored from the boundary thereafter.

Abstract: A storage device includes; a nonvolatile storage including a first region and a second region, a storage controller controlling operation of the nonvolatile storage, and a buffer memory connected to the storage controller. The storage controller stores user data received from a host device in the second region, stores metadata associated with management of the user data and generated by a file system of the host device in the first region, loads the metadata from the first region to the buffer memory in response to address information for an index node (inode) associated with the metadata, and accesses the target data in the second region using the metadata loaded to the buffer memory.

Abstract: An in-place data recovery method and system include receiving a user request to restore a virtual machine to a version corresponding to a first point in time, identifying a first snapshot of the virtual machine based on the user request, generating a second snapshot of the virtual machine, identifying a second data block in the second snapshot that includes modified data derived from data content of a first data block in the first snapshot, generating reverse incremental backup data including the first data block, and restoring the virtual machine in-place based on the reverse incremental backup data.

Abstract: A processor having a functional slice architecture is divided into a plurality of functional units (“tiles”) organized into a plurality of slices. Each slice is configured to perform specific functions within the processor, which may include memory slices (MEM) for storing operand data, and arithmetic logic slices for performing operations on received operand data. The tiles of the processor are configured to stream operand data across a first dimension, and receive instructions across a second dimension orthogonal to the first dimension. The timing of data and instruction flows are configured such that corresponding data and instructions are received at each tile with a predetermined temporal relationship, allowing operand data to be transmitted between the slices of the processor without any accompanying metadata. Instead, each slice is able to determine what operations to perform on received data based upon the timing at which the data is received.