Patents Examined by J. Peikari
  • Patent number: 6594728
    Abstract: A two-way cache memory having multiplexed outputs and alternating ways is disclosed. Multiplexed outputs enable the cache memory to be more densely packed and implemented with fewer sense amplifiers. Alternating ways enable two distinct cache access patterns. According to a first access pattern, two doublewords in the same way may be accessed simultaneously. Such access facilities the leading of data into main memory. According to a second access pattern, two doublewords in the same location but in different ways may be accessed simultaneously. Such access facilitates the loading a particular word into a register file.
    Type: Grant
    Filed: March 7, 1997
    Date of Patent: July 15, 2003
    Assignee: MIPS Technologies, Inc.
    Inventor: Kenneth C. Yeager
  • Patent number: 6112284
    Abstract: A memory controller having a data strobe that tracks the column access strobe signal in a computer system having Extended Data Out (EDO) DRAMs. The data strobe signal follows, by a predetermined delay, the column access strobe signal, and therefore any skew in the column access strobe signal is inherently included within the data strobe signal. As a result, the data can be latched out, responsive to said data strobe signal, at approximately the center of the valid window.
    Type: Grant
    Filed: December 30, 1994
    Date of Patent: August 29, 2000
    Assignee: Intel Corporation
    Inventors: George R. Hayek, Joe M. Nardone, Aniruddha Kundu, Kuljit S. Bains
  • Patent number: 5978887
    Abstract: A two-way cache memory having multiplexed outputs and alternating ways is disclosed. Multiplexed outputs enable the cache memory to be more densely packed and implemented with fewer sense amplifiers. Alternating ways enable two distinct cache access patterns. According to a first access pattern, two doublewords in the same way may be accessed simultaneously. Such access facilitates the leading of data into main memory. According to a second access pattern, two doublewords in the same location but in different ways may be accessed simultaneously. Such access facilitates the loading a particular word into a register file.
    Type: Grant
    Filed: March 7, 1997
    Date of Patent: November 2, 1999
    Assignee: Silicon Graphics, Inc.
    Inventor: Kenneth C. Yeager
  • Patent number: 5956744
    Abstract: A multilevel hierarchical least recently used cache replacement priority in a digital data processing system including plural memories, each memory connected to said system bus for memory access, a memory address generator generating addresses for read access to a corresponding of the memories and a memory cache having a plurality of cache entries, each cache entry including a range of addresses and a predetermined set of cache words. During each memory read the comparator compares the generated address with the address range of each cache entry. If there is a match, then the cache supplies a cache word corresponding to the least significant bits of the generated address from the matching cache entry. If there is no such match, the generated address is supplied to the memories and a set of words is recalled corresponding to the generated address. This set of words replaces a least recently used prior stored memory cache entry having the lowest priority level.
    Type: Grant
    Filed: September 6, 1996
    Date of Patent: September 21, 1999
    Assignee: Texas Instruments Incorporated
    Inventors: Iain Robertson, Karl M. Guttag, Eric R. Hansen
  • Patent number: 5956274
    Abstract: A random access memory chip comprising static random access storage elements, word lines and bit lines connected to the storage elements, a sense amplifier connected to each of the bit lines, a separate processor element connected to each of the sense amplifiers, apparatus for addressing a word line, and apparatus for applying a single instruction to the processor elements, whereby the instructed processor elements are enabled to carry out a processing instruction in parallel on separate bits stored in the storage elements of the addressed word line. A method of operating a digital computer comprising in one operation cycle, addressing a memory, reading each of a row of data from the memory in parallel, and performing an operation function on each bit of the data in parallel to provide a result.
    Type: Grant
    Filed: July 24, 1996
    Date of Patent: September 21, 1999
    Assignee: Mosaid Technologies Incorporated
    Inventors: Duncan G. Elliott, W. Martin Snelgrove
  • Patent number: 5937434
    Abstract: Methods of allocating, writing, reading, de-allocating, re-allocating, and reclaiming space within a nonvolatile memory having a bifurcated storage architecture are described. A method of storing an object within a managed object space of the nonvolatile memory includes the step of determining an object class for the object. Objects of a first class are stored contiguously proceeding from a first end towards a second end of the managed object space to form a first class of space. Objects of a second class are stored contiguously proceeding from the second end towards the first end of managed object space to form a second class of space. A header identifying the object is stored at a bottom of the first class of space. The object is stored at a selected one of the bottom of the first class of space and a bottom of the second class of space in accordance with the object class.
    Type: Grant
    Filed: February 14, 1997
    Date of Patent: August 10, 1999
    Assignee: Intel Corporation
    Inventors: Robert N. Hasbun, David A. Edwards, Andrew H. Gafken
  • Patent number: 5930830
    Abstract: A system and method are provided which significantly speed up the ability to reassemble network message transfer units (MTUs) using existing virtual memory systems. Discontiguous physical pages are rearranged in a continuous format in virtual memory by manipulating virtual page pointers in a hardware memory page table. The hardware memory page table provides any necessary virtual-to-real address translations during the execution of a process.
    Type: Grant
    Filed: January 13, 1997
    Date of Patent: July 27, 1999
    Assignee: International Business Machines Corporation
    Inventors: Abraham Mendelson, Ronald Mraz, Lucas Aaron Womack
  • Patent number: 5920890
    Abstract: A loop cache (26) is used in a data processing system for supplying instructions to a CPU to avoid accessing a main memory. Whether instructions stored in the loop cache can be supplied to the CPU is determined by a distributed TAG associated with the instruction address computed by the CPU. The instruction address includes an LCACHE index portion (42), an ITAG portion (44), and a GTAG (46). LCACHE index (42) selects corresponding locations in each of an ITAG array (50), an instruction array (52), and a valid bit array (54). A stored GTAG value (48) is chosen irrespective of where LCACHE index (42) is pointing. The GTAG portion of the instruction address (40) is compared to the stored GTAG value (48). The ITAG portion (44) of instruction address (40) is compared with the indexed ITAG of the ITAG array (50). If both the GTAG and ITAG compare favorably, the instruction is supplied from the loop cache to the CPU, rather than from main memory.
    Type: Grant
    Filed: November 14, 1996
    Date of Patent: July 6, 1999
    Assignee: Motorola, Inc.
    Inventors: William C. Moyer, Lea Hwang Lee, John Arends
  • Patent number: 5913028
    Abstract: A direct data delivery system and method for use in client/server environments for direct transfer of data files between Peer I/O Devices so as to allow reading from or writing to file servers with minimal burden to the file server's central processing units, to alleviate congestion on data buses and delay of real time data delivery. The instant invention provides high bandwidth server solutions based upon hardware and software components that enable direct data/file transfers among peer I/O devices, including but not limited to, directed data transfers between storage and network I/O devices.
    Type: Grant
    Filed: October 6, 1995
    Date of Patent: June 15, 1999
    Assignee: Xpoint Technologies, Inc.
    Inventors: Frank Wang, Jeffrey S. Robertson, Nuggehalli N. Gopal, Charles J. Pheterson, Michael S. Goldflam
  • Patent number: 5909691
    Abstract: For use with a computer system having an intelligent mass storage disk array subsystem, including a microprocessor controller, a method for the distribution of data within the disk array based upon logical commands issued by the computer system. The disk controller reads a logical command and translates the commands into multiple drive specific commands, including drive physical parameter information such as head, sector and cylinder selection. The calculation of these physical parameters is based upon a number of factors including the operating system installed in the computer system, the type of interleave scheme, if any, specified by the computer system configuration, and disk specific parameters. The physical drive requests are then placed in a queue and executed by the microprocessor controller.
    Type: Grant
    Filed: December 20, 1996
    Date of Patent: June 1, 1999
    Assignee: Compaq Computer Corporation
    Inventors: Stephen M. Schultz, David S. Schmenk, E. David Neufeld, David L. Grant, David L. Flower
  • Patent number: 5905909
    Abstract: A synchronous dynamic random access memory (SDRAM) device having a master control circuit for accepting a first command and a second command and having an initialization and reprogramming circuit. The master control circuit generates and initialization signal in response to the first command and generates a reprogramming signal in response to the second command. The initialization and reprogramming circuit responds to the initialization signal to control initial programming of a control operation feature and responds to the reprogramming signal to control a reprogramming of the control operation feature.
    Type: Grant
    Filed: January 13, 1997
    Date of Patent: May 18, 1999
    Assignee: Micron Technology, Inc.
    Inventors: Brett Williams, Scott Schaefer
  • Patent number: 5895486
    Abstract: A method and system for reducing bus traffic in a multiple processor system having a shared memory and processor related private caches. Store multiple word instructions are evaluated to determine whether a full cache line is to be modified. If the full cache line is to be stored, a cache line kill is issued on the system bus and the cache line is written to the cache. Any store operation of single word, or multiple words extending over portions of a cache line, invokes conventional memory coherence processes.
    Type: Grant
    Filed: December 20, 1996
    Date of Patent: April 20, 1999
    Assignee: International Business Machines Corporation
    Inventor: Rajesh Bhikhubhai Patel
  • Patent number: 5896551
    Abstract: A synchronous dynamic random access memory (SDRAM) device having a master control circuit for accepting a first command and a second command and having an initialization and reprogramming circuit. The master control circuit generates and initialization signal in response to the first command and generates a reprogramming signal in response to the second command. The initialization and reprogramming circuit responds to the initialization signal to control initial programming of a burst control operation feature and responds to the reprogramming signal to control a reprogramming of the burst control operation feature.
    Type: Grant
    Filed: April 15, 1994
    Date of Patent: April 20, 1999
    Assignee: Micron Technology, Inc.
    Inventors: Brett Williams, Scott Schaefer
  • Patent number: 5895489
    Abstract: A memory management system for a computer, where cache coherency between a descriptor cache and data cache is preserved through an inclusion bit mechanism. In one embodiment, an inclusion bit is set for a descriptor cached in a data cache corresponding to a descriptor cached in a descriptor cache such that the association between the descriptors is indicated. Whenever a descriptor in the data cache with a set inclusion bit is altered, the entire descriptor cache is flushed by virtue of the set inclusion bit. Furthermore, in the same embodiment, a valid bit is set for a descriptor in the data cache which is cached from the descriptor table. Whenever a descriptor in the descriptor table, which has a valid bit set in the data cache, is modified, the valid bit is reset. And if the same descriptor with its valid bit reset has a set inclusion bit, then the entire descriptor cache is flushed.
    Type: Grant
    Filed: October 16, 1991
    Date of Patent: April 20, 1999
    Assignee: Intel Corporation
    Inventors: Gary N. Hammond, Pradeep Dubey, Mustafiz R. Choudhury
  • Patent number: 5893921
    Abstract: A method for maintaining memory coherency in a data processing system is disclosed. The data processing system includes a memory system having a dual bus memory controller, which is coupled to a first bus through a first bus master and a second bus coupled to a second bus master. The method maintains memory coherency by snooping across either the first or second bus for attributes on an address/data multiplex bus in the data processing unit. To determine when a snoop operation is required, the system begins by requesting access to either of the two buses through the dual bus memory controller. Once the control of the bus has been granted upon request data is transferred using the master bus controller. It is upon the receipt of an invalid data signal while transferring data across the bus that the snoop activity begins. The snoop is injected only after an invalid data signal is received and a last snoop injection can occur only before a last read data is read.
    Type: Grant
    Filed: February 10, 1995
    Date of Patent: April 13, 1999
    Assignee: International Business Machines Corporation
    Inventors: Timothy Bucher, Douglas Christopher Hester, John Victor Sell, Cang N. Tran
  • Patent number: 5875464
    Abstract: The traditional computer system is modified by providing, in addition to a processor unit, a main memory and a cache memory buffer, remapping logic for remapping the cache memory buffer, and a plurality of registers for containing remapping information. With this environment the cache memory buffer is divided into segments, and the segments are one or more cache lines allocated to a task to form a partition, so as to make available (if a size is set above zero) of a shared partition and a group of private partitions. Registers include the functions of count registers which contain count information for the number of cache segments in a specific partition, a flag register, and two register which act as cache identification number registers. The flag register has bits acting as a flag, which bits include a non-real time flag which allows operation without the partition system, a private partition permitted flag, and a private partition selected flag.
    Type: Grant
    Filed: March 18, 1996
    Date of Patent: February 23, 1999
    Assignee: International Business Machines Corporation
    Inventor: David Brian Kirk
  • Patent number: 5875457
    Abstract: A method and apparatus for dynamically expanding an N drive RAID set to an M drive RAID set while maintaining data integrity, where the M drive RAID set includes one or more new drives. The method comprises the steps of identifying a destructive zone in the N drive RAID set including destructive zone data. Thereafter the destructive zone data is mirrored in the M drive RAID set by copying it to a free location in the N drive RAID set and to a location in a new drive in the M drive RAID set. Finally, the N drive RAID set is expanded to an M drive RAID set. Data integrity is assured in the N drive RAID set during migration by maintaining mirrored destructive zone data until the expansion step has completed migration of the destructive zone of the N drive RAID set.
    Type: Grant
    Filed: October 8, 1996
    Date of Patent: February 23, 1999
    Assignee: Mylex Corporation
    Inventor: Amir Shalit
  • Patent number: 5875479
    Abstract: A volume-to-volume copy method on a DASD storage subsystem concurrent with host CPU application execution and referencing of data on a primary. In this method, updates to data made on a primary volume after the element was copied during a first pass will be deferred and copied only during a second pass rather than interrupting the first pass. This accumulation and deferral of updates to a second pass shortens the volume copy time and reduces application referencing delay.
    Type: Grant
    Filed: January 7, 1997
    Date of Patent: February 23, 1999
    Assignee: International Business Machines Corporation
    Inventors: Lawrence Carter Blount, Carol Santich Michod
  • Patent number: 5875352
    Abstract: An on-chip cache memory is used to provide a high speed access mechanism to frequently used channel state information for operation of a DMA device that supports multiple virtual channels in a high speed network interface. When an access to a particular channel state is performed, e.g., by a host processor or the DMA device, the cache is first accessed and if the state information is not located currently in the cache, external memory is read and the state information is written to the cache. As the cache does not store all the states stored in external memory, replacement algorithms are utilize to determine which channel state information to remove from the cache in order to provide room to store a recently accessed channel. A doubly linked list is used to track the most recently used channel. As cached channel information is accessed, the corresponding entry is moved to the top of the list. The doubly linked list provides a rapid apparatus and method for updating pointers to the cache.
    Type: Grant
    Filed: November 3, 1995
    Date of Patent: February 23, 1999
    Assignee: Sun Microsystems, Inc.
    Inventors: Denton E. Gentry, Rasoul M. Oskouy
  • Patent number: 5875486
    Abstract: A semiconductor memory device comprises a memory cell group comprising a plurality of memory cells arranged in matrix; a specification circuit for specifying sequentially memory cells addressed by consecutive addresses in the memory cells, and for enterring them in an active state; a data input/output (I/O) circuit for performing a data read-out/write-in operation (data I/O operation) for the consecutive memory cells specified by the specification circuit under a control based on a read-out/write-in signal provided from an external section; a counter circuit for counting the number of cycles of a basic clock signal provided from an external section; and a controller for receiving at least one or more specification signals provided from an external section, for outputting a control signal per specification signal for specifying a particular cycle as a starting cycle to count the number of the cycles of the basic clock signal, and for instructing the counter circuit to count the number of counts of the basic cl
    Type: Grant
    Filed: August 15, 1997
    Date of Patent: February 23, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Haruki Toda, Shozo Saito, Kaoru Tokushige