Abstract: An addressable memory having: a buffer memory adapted for coupling to a bus; a random access memory coupled to the buffer memory; an internal clock; and, a logic network, coupled to the bus and configured to transferring data among the buffer memory, the random access memory and the bus in response to clock signals produced by the internal clock and clock pulses provided on the bus. In a preferred embodiment, the buffer memory includes a first-in/first out (FIFO). A data storage system wherein a main frame computer section having main frame processors for processing data is coupled to a bank of disk drives through an interface. The interface includes: a bus; a controller; and, an addressable memory. The controller and addressable memories are interconnected through the bus. The addressable memory includes a master memory unit and a slave memory unit.

Abstract: A multiported random access memory (RAM) system comprising a RAM having a data port and an address and control port, plural data buffers each having a bidirectional input port and a bidirectional output port, a data bus connecting the output ports of the data buffers and the data port of the RAM, a multiplexer having plural address and control inputs and an address and control output, the address and control output being connected to the address and control port of the RAM, each of the address and control inputs for receiving address and control data associated with data stored in a specific buffer, a timing apparatus connected to each of the buffers and to a control input of the multiplexer for separately enabling the multiplexer to pass address and control data therethrough to the address and control port of the RAM or to receive data from the data port of the RAM, whereby the bidirectional data input ports of the buffers and each of the corresponding address and control input ports forms a separate time sh

Abstract: Methods and associated apparatus operable in a RAID subsystem to improve the speed and flexibility of initializing the subsystem by storing configuration and identification information in a reserved area on each disk drive in the subsystem. The reserved area on each disk drive of the disk array contains a unique identifier to identify the particular disk drive from all others and further contains group configuration information regarding all groups in which the particular disk drive is a member. The configuration and identification information is generated and written to each disk drive in the disk array when the particular disk drive is configured so as to be added or deleted from groups of the subsystem. Upon subsystem reset (e.g. power on reset or other reset operations), the RAID controller in the subsystem determines the proper configuration of the RAID groups despite temporary unavailability or physical relocation of one or more disk drives in the disk array.

Abstract: A cache locking mechanism is implemented so that portions of the cache may be locked to protect critical instructions or data residing within the cache. Such a cache may be associated with a processor chip, coupled to a data processing system. The cache locking mechanism forces de-allocation of cache entries to the unlocked section of the cache. However, allocation of cache entries is performed regardless of whether or not an entry resides within the locked portion, provided that there exists invalid entries within the locked portion.

Abstract: An apparatus and method for transferring data sets between a storage controller and a number of daisy chained main memories on separate circuit elements at high speed. Each main memory has coupled control logic which receives a data set from the storage controller, latches and retransmits the data set to the next main control logic and coupled memory, which next control logic repeats the process, and which can be continued through a number of coupled control logic units and main memories. A data set includes a header with an address range and function information. If data is to be sent from the storage controller it is appended to the header. Each storage controller compares the address range with the address range of the coupled memory, and if within the address range and for a write, will store the appended data in the header address in the coupled memory.

Abstract: A recording and reproducing apparatus of the present invention has reproduction change detector for receiving information indicative of a detection of a reproduction operation from an in-reproduction detector, and a record change detector for receiving the information indicative of the detection of the reproduction operation of recording parts from in-record detector, thereby having excellent operability by simple switching operation.

Abstract: A method for writing software into a programmable memory within a peripheral apparatus initiated by a host computer is provided. The host computer issues a software write command and the peripheral apparatus includes a microcontroller connected to the host computer via an interface. A data line and an address line are provided to connect the microcontroller and the programmable memory. The method comprises the following steps: (1) providing a supervisory program within the programmable memory or the microcontroller, the supervisory program including a software write instruction; (2) the microcontroller executing the software write instruction and down-loading the software from the host computer via the interface; and (3) via the data and address line, performing the write operation of the control software to the programmable memory.

Abstract: A method for initially programming a synchronous dynamic random access memory (SDRAM) device to have a first control operating option in response to a first command and for reprogramming the SDRAM device to have a second control operating option in response to a second command without interrupting the active state of the memory array.

Abstract: A check is made to determine if a copy of a cache line is currently resident in the level-one data cache of a microprocessor system. If, in response to the check, it is determined that a copy of such cache line in fact is not currently resident, the cache line is created as the least-recently used cache line. Then, for set-associative data caches, the next used of the associative set will replace the most recently zeroed line. In this way, zeroing operations can replace only one .div. (number of associative sets) of the data cache for zeroing operations, thereby leaving the most frequently used data intact. By doing so, the data-cache is not wasted on zeroed cache lines which may be infrequently reused from the data cache, thereby significantly improving system performance. In other words the net effect is to reduce probability of data cache misses on subsequent instructions because more of the cache is thereby made available for more frequently reused data.

Abstract: A method and apparatus for efficiently reading a day clock and storing the value into main storage. An advantage is that the memory storage command can request the main storage control to read a current day clock value and store the value into a main storage location specified by the requesting processor while allowing the requesting processor to continue processing other commands. A further advantage is that the requesting processor does not have to wait for the return of a day clock value or the generation of a main storage write request which may reduce the number of main storage I/O bus requests and bus transfer cycles over that normally required to transfer the day clock value to the requesting processor and then back to main storage.

Abstract: A multiple FIFO array which does not use numerous single FIFO devices is provided. The multiple FIFO array includes a memory partitioned into a plurality of N sections, each section corresponding to one of N FIFOs. The memory has a write address input, write strobe input, data input, read address input, read strobe and data output. Also included is a plurality of N write pointer registers, a write multiplexer having N write inputs, a write output and a write select input, a plurality of N read registers and a read multiplexer. Each write pointer register corresponds to one of N FIFOs and each write pointer register holds the write address corresponding to one of N FIFOs. The N write inputs of the write multiplexer are coupled to the output of the plurality of N write pointer registers, the write output is coupled to the write address input in the memory and the write select input couples one of the N write inputs to the write output.

Abstract: An improved method for performing state cache line replacement operations in a multiprocessor computer system including plurality if data cache memories, a shared system memory, a state cache memory, and employing a centralized/distributed directory-based cache coherency system for maintaining consistency between lines of memory within the shared system memory and the plurality of data cache memories.

Abstract: A system for exchanging digital data among a plurality of hand-held computer devices. Digital signals are written by a first hand-held device to a mini-cartridge that mini-cartridge is inter-operable among a class of hand-held devices, each of which is equipped with a mini-disk drive. A common digital data format is employed to further facilitate exchange of data between devices.

Abstract: An interleaved data cache array which is divided into two subarrays. Each subarray includes a plurality of cache lines wherein each cache line includes a selected block of data, a parity field, a content addressable field containing a portion of an effective address for the selected block of data, a second content addressable field contains a portion of the real address for the selected block of data and a data status field. By utilizing two separate content addressable fields for the effective address and real address offset and alias problems may be efficiently resolved. The data cache is preferably arranged as an eight way set-associative cache wherein each congruence class includes up to eight entries having identical low order address bits.

Abstract: Data line loading on high density modules with multiple DRAMs is minimized permitting the maximum memory density of systems of otherwise limited density to be increased without an ensuing performance degradation due to data line capacitive loading. There are two parts to the solution of reducing data line capacitance to an acceptable system limit. The first part involves designing a memory module with in-line bus switches. The bus switches are placed between the module tabs (system) and random access memory devices and are either in a high impedance (off) or active state. When in the high impedance state, the effective loading of the module is that of the bit switch device. The second part of the solution is to embed logic into an application specific integrated circuit (ASIC) that monitors bus activity and controls activation of the bus switches.

Abstract: An SDRAM offering an increased operating speed and needing a limited area for layout is provided. In the synchronous DRAM, at least part of the signal processing to be executed continually is divided into a plurality of steps, the plurality of steps are executed concurrently in synchronization with an external clock applied externally, and thus the operating speed is increased. The synchronous DRAM comprises a plurality of pipes (i.e.

Abstract: Discovery/layout software configures a general purpose computer system to act as a management station using an industry standard SNMP protocol. The discovery/layout software has a discovery mechanism and a layout mechanism which, in combination, permit the discovery/layout software to provide various submaps to a display for illustrating network topology, which includes devices and device interconnections of a network. The submaps correspond to various hierarchical views of a network. Significantly, one or more filtering systems are provided in the discovery/layout software for filtering objects to be displayed within the submaps. The filtering systems reduce clutter in the submaps, reduce memory usage and associated expense, and reduce interprocess communication (context switching) to achieve higher performance.

Abstract: An integrated circuit (IC) architecture includes a bit mask register (BMR) and a serial access memory (SAM) which share address decode and clock circuitry within a multiport random access memory chip. The integrated circuit also includes a random access memory and circuitry for performing a bit masked transfer between the serial access memory and the random access memory. Mask data may be clocked into the bit mask register, which may be cleared upon completion of a data transfer between the random access memory and the serial access memory. The mask data may also be inverted upon being transferred between the random access memory and the bit mask register. This architecture provides CLEAR and TRUE or COMPLEMENT masked transfer output ability in the BMR, and has utility in real-time video windowing in memory mapped computer graphics.

Abstract: A synchronous burst SRAM device comprising an SRAM core having a memory array, write drivers, sense amplifiers, and I/O buffers; an address register for receiving addresses for the memory array in the SRAM core; a burst address generator coupled to the address register for rapidly generating additional addresses using at least one address bit stored in the address register; an input for receiving an external address signal indicating that an external address is ready to be loaded into the address register; three chip enable inputs for receiving chip enable signals; chip enable and select logic coupled to the three chip enable inputs to perform the dual tasks of (1) selectively enabling or disabling the synchronous burst SRAM device and (2) selectively permitting access to the SRAM core when the SRAM device is enabled in accordance with a boolean function of the chip enable signals at the three chip enable inputs, the chip enable and select logic outputting an SRAM core enable signal resulting from the boolean

Abstract: A cache system has a large master cache and smaller slave caches. The slave caches are coupled to the processor's pipelines and are kept small and simple to increase their speed. The master cache is set-associative and performs many of the complex cache management operations for the slave caches, freeing the slaves of these bandwidth-robbing duties. Only the slave caches store sub-line valid bits with all cache lines; the master cache has only full cache lines valid. During a miss from a slave cache, the slave cache sends its sub-line valid bits to the master cache. The slave's sub-line valid bits are loaded into a request pipeline in the master cache. As requests are fulfilled and finish the pipeline, its address is compared to the addresses of all other pending requests in the master's pipeline. If another pending request matches the slave's index and tag, its sub-line valid bits are updated by setting the corresponding sub-line valid bit for the completing request's sub-line.