Abstract: A method and apparatus for dynamically expanding an N drive RAID set to an M drive RAID set while maintaining data integrity, where the M drive RAID set includes one or more new drives. The method comprises the steps of identifying a destructive zone in the N drive RAID set including destructive zone data. Thereafter the destructive zone data is mirrored in the M drive RAID set by copying it to a free location in the N drive RAID set and to a location in a new drive in the M drive RAID set. Finally, the N drive RAID set is expanded to an M drive RAID set. Data integrity is assured in the N drive RAID set during migration by maintaining mirrored destructive zone data until the expansion step has completed migration of the destructive zone of the N drive RAID set.

Abstract: A data cache configured to perform store accesses in a single clock cycle is provided. The data cache speculatively stores data within a predicted way of the cache after capturing the data currently being stored in that predicted way. During a subsequent clock cycle, the cache hit information for the store access validates the way prediction. If the way prediction is correct, then the store is complete. If the way prediction is incorrect, then the captured data is restored to the predicted way. If the store access hits in an unpredicted way, the store data is transferred into the correct storage location within the data cache concurrently with the restoration of data in the predicted storage location. Each store for which the way prediction is correct utilizes a single clock cycle of data cache bandwidth. Additionally, the way prediction structure implemented within the data cache bypasses the tag comparisons of the data cache to select data bytes for the output.

Abstract: A nonvolatile memory having a plurality of individually erasable blocks is used to store sectors of a file. A method of overwriting the file includes the step of receiving a frame of data. The logical sector that the frame is to be written to is determined. The logical sector corresponds to a first sector located at a first offset in a first block of the nonvolatile memory. The first block also has an associated first logical block number. The frame of data is written to a second sector. The second sector is located at a second offset in a spare block. The first and second offsets are identical. The logical block number of the spare block is updated to be the same as the first logical block number.

Abstract: A method enables a host processor, which employs variable length (VL) records, to transparently communicate with disk storage which employs fixed length (FL) sectors for storage of the VL records.

Abstract: A scalable symmetric multiprocessor data-processing system is disclosed. The symmetric multiprocessor data-processing system includes multiple processing units and a system memory. Each of the processing units includes a cache memory for storing a subset of data contained within the system memory. A cache controller is included within each one of the processing units for controlling an associated cache memory. The cache controller contains a mode select to allow an associated cache memory to be selectively operated under either a first mode or a second mode. Furthermore, the symmetric multiprocessor data-processing system also includes a multiple of partial system memories, wherein each of the partial system memories is associated with one of the processing units such that an aggregate of contents within all of the partial system memories forms the system memory.

Abstract: A method enables a host processor, which employs variable length (VL) records, to communicate with disk storage which employs fixed length (FL) sectors for storage of the VL records.

Abstract: A method and a system for the interleaving of real-time files so as to form an interleaved combination for storage or transmission. They can be used for a multimedia application in which real-time files containing audio and/or video information are combined so as to form a real-time file for use by the application. The invention utilizes a structure in which the real-time files are stored in dependence on their period in conformity with a given space-saving criterion. Subsequently, on the basis of the structure, an interleaved combination is formed in which the number of empty positions in the combination is limited.

Abstract: A command is issued from a processing unit to an on-line storage unit and transferred from the on-line storage unit to a back-up storage unit. The received commands are processed in the respective storage units. An overhead of the on-line storage unit is reduced in a hot stand-by system. Storage contents of the on-line storage unit and the back-up storage unit are made coincident in a structure having a plurality of processing units, where the on-line storage unit and the back-up storage unit are connected through a channel device.

Abstract: A circuit for controlling which set of a four-way set associated cache memory receives data for storage includes a memory array for storing six bits of information representative of the relative use of the four sets within the cache memory. Least recently used (LRU) update logic operates in conjunction with bit write drivers to generate and write the six bits of information to the memory array in a single access cycle. Replace logic reads the stored information from the memory means and produces output signals therefrom. The output signals are used to control into which of the four sets data is written. Error detection and fault tolerant embodiments are also disclosed as is a method of controlling which set of a four-way set associative cache memory receives data for storage.

Abstract: A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU).

Abstract: A record/playback device for use with a removable, interchangeable, flash memory recording medium which enables noise dampened recording of voice data and CD quality stereo recording of music data. The device includes a port for receiving a flash memory module which can record data according to industry standard formats to enable the transfer of data to and from personal computers through swapping of flash memory media. Alternative forms of data input and output also include implementation of a barcode reader and an infra-red transceiver for the transfer of data to and from the device.

Abstract: A method and apparatus improves data retention in a nonvolatile writeable memory. A first group of memory cells is identified as having a stored charge over a first threshold. A subset of the first group of memory cells having a stored charge less than a second threshold is determined. The subset of the memory cells is programmed until each of the memory cells of the subset has a stored charge over the second threshold.

Abstract: A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU).

Abstract: A memory configuration system including least one of plural control lines and address lines from a memory controller to attached memory may be used as a capacity indicating line, a presence indicating line, and/or a memory type indicating line. With the assistance of coding circuitry dedicated to each mounting region, capacity, presence, and type information for the attached memory module(s) may be communicated via their respective lines. This information is used by the controller to establish a memory configuration.

Abstract: For a write request from the CPU, the control unit selects a specific disk unit in the disk unit group for the immediate writing of data. In a second kind of load distribution a disk unit is selected to execute read and staging other than the above-mentioned specific disk.

Abstract: A fast data write method for transferring data from a computer system to a storage system in a single tasking operating environment. A fast write flag is set in order to reflect the ready or busy state of the storage system. A processor of the computer system ends the storage data write cycle as soon as the data has been sent to the storage system. Thus, the processor does not waste any processor time after the data is sent, and transfers are made without compromising integrity of the data.

Abstract: Recording data is recorded on a CD-ROM so as to satisfy a relationship expressed as W.gtoreq.D and W>m where W is the data length of recording data recorded on the CD-ROM, D is the data length of effective data useful for being accessed (system area, file groups selected when data is edited and retrieval data such as volume descriptor, path table and directory) and m is the maximum recordable data length of a blank disk of a CD-ROM to which data recorded on the CD-ROM is copied. Then, when the relationship between the recording data length W and the effective data length D is expressed by W>D, said recording data contains randomly quasi-data useless for being accessed. Further, a part (e.g., path table) of the retrieval data is arranged at the end of the recording data upon recording. Thus, an illegal copy from the CD-ROM to a blank disk becomes substantially useless, thereby making it possible to effectively protect a copyright of the CD-ROM.

Abstract: A fault tolerant computer which executes the cache flush operation at a high speed and has the real time characteristic. A processor module 301 is equipped with a cache memory so that the entry address of the updated cache block within the cache memory is stored in a stack. The cache flush is effected only with respect to the entry address in the stack when a recovery-point setting condition due to a timer or the like is satisfied. A memory module 303 has an arrangement doubled in the same storage physical space and is equipped with a buffer memory for temporarily storing the transferred cache block, so that the cache block is simultaneously transferred to a pair of buffer memories.

Abstract: A computer system which utilizes processor boards including a first level cache system integrated with the microprocessor, a second level external cache system and a third level external cache system. The second level cache system is a conventional, high speed, SRAM-based, writeback cache system. The third level cache system is a large, writethrough cache system developed using conventional DRAMs as used in the main memory subsystem of the computer system. The three cache systems are arranged between the CPU and the host bus in a serial fashion. Because of the large size of the third level cache, a high hit rate is developed so that operations are not executed on the host bus but are completed locally on the processor board, reducing the use of the host bus by an individual processor board. This allows additional processor boards to be installed in the computer system without saturating the host bus. The third level cache system is organized as a writethrough cache.

Abstract: The present invention provides for executing load instructions with a processor having a non-blocking cache memory, wherein individual load operations are dispatched to the cache memory and the cache memory signals the prevent the load operation from being sent to external memory when the load operation misses the cache memory and there is already a currently pending bus cycle to the same cache line. This helps reduce bus traffic on the external bus.