Abstract: A circuit comprising a number of address range registers and complimentary decoding/matching circuits is provided to a processor for determining the memory type of a physical address, thereby allowing memory type to be determined as soon as the physical address is available in an execution stage preceding cache access. Additionally, a memory type field is provided to each address translation lookaside buffer entry of the data and instruction memory subsystem for storing the determined memory type. The memory type determination circuit is disposed in the page miss handler, thereby allowing memory type to be determined at the same time when the physical address is determined.

Abstract: In an information storage system having at least a storage medium which includes a plurality of storage areas. Each storage area is associated with one logical drive. Using a control device and in conjunction with an I/O control device and a memory, the system can process coexisting code and image information to permit a designated logical drive to access an area of the storage areas that corresponds to the designated logical drive according to correspondence relation information.

Abstract: A data transfer controller for transferring data between a memory and a peripheral unit enhances the efficiency of the DMA transfer by performing data transfer a predetermined number of times for each transfer request from the peripheral unit. The data transfer controller comprises a first register for storing address information for accessing a source area storing data to be transferred, a second register for storing first information relative to a number of data units ready to be transferred, and a third register for storing second information relative to a number of times by which a data transfer is performed in response to each transfer request from the peripheral unit. A data transfer from the source area to a destination area is performed a number of times designated by the second information in response to each transfer request. A transfer completion signal is generated when the number of data units transferred reaches the number designated by the first information.

Abstract: A data processing system for performing square operations includes a data processor such as a digital signal processor (DSP) and a memory system. The DSP has two data paths for fetching two operands of an instruction from locations specified by two addresses, which may be required for an operation such as a multiply operation. A fetch from the second data path is delayed in response to a wait signal. The memory system includes at least two memory portions. Data from the two memory portions are multiplexed onto the two data paths in response to a first portion of the respective addresses. If the first portions of both addresses are equal, and if second portions are unequal, the wait signal is activated. If the second portions of the addresses are equal, such as during a square operation, the wait signal is inactive and data is simultaneously read by both data paths.

Abstract: A microcomputer includes a layered memory having a higher layer for storing a series of instructions forming a program to be executed by the microcomputer and a lower layer, having an upside layer accessed by ID information in the instructions stored in the higher layer memory, and a downside layer, accessed by the upside layer, having a sequence of storage locations storing code data for controlling the execution unit to calculate effective addresses.