Abstract: A cache memory operates in a first mode, in which a cache hit occurs, and in a second mode, in which a cache miss occurs. A data processor operates in a first state in which instructions are accessed from memory and in a second state in which data is accessed from memory. Cache memory has a condition setting circuit which distinguishes instruction caching from a data caching. The processor sends an access-type signal which is compared with the access-type set in the condition setting circuit. When the access-type signal does not coincide with the contents of the condition setting circuit, a third state is declared which links the main memory and cache memory.

Abstract: A method is described for logically isolating a cache memory bank from the other cache memory banks, as well as from the associated disk drive system and the computer system, while allowing effective use of the remaining cache banks. Linked lists of pointers to free space in a given cache bank are located entirely within the bank; therefore, failure of, or removal of, a cache bank does not prevent the computer and disk drive system from utilizing the free space in the remaining banks. The implementation of the method is such that initialization of all cache memory banks may also be efficiently performed.

Abstract: CPU system performance is improved by reducing the time required to complete a DRAM access by microprocessors such as the 386DX, 386SX and 80286 by incorporating a programmable DRAM controller therewith which permits consecutive DRAM accesses to average N+0.5 processor wait states. The half wait state average is obtained by forcing the system CPU to measure wait states in processor clock time units which are twice the period of an independent clock in the DRAM controller which, in turn, triggers RAS and CAS assert and de-assert. RAS or CAS is thus able to assert 1/2 processor clock period earlier in one memory cycle relative to the last. Early assert time also provides for an early de-assert time so that data can be transferred to/from the DRAM more quickly than previously possible.

Abstract: A structure and a method for directing execution of instructions are provided in a microprocessor with an on-chip cache memory. In one embodiment, the microprocessor provides a debug mode, which is activated by a signal on a mode pin. In the debug mode, when a signal is received on a second mode pin indicating that an instruction is to be provided on the memory bus is desired, a cache miss is generated at the next instruction fetch. Thus, the processor is forced to fetch the next instruction from main memory. The instruction is then provided on the memory bus as though it is fetched from the main memory in response to the read cycle resulting from the cache miss.

Abstract: A semiconductor memory device has an address generating system for a burst access mode, and the address generating system previously generates the next internal address through an exclusive-OR operation during supply of a present internal address, thereby quickly changing the internal address in synchronism with an internal clock signal.

Abstract: A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU).

Abstract: The invention is a system and method for accessing a plurality of memory banks. The system includes a number of memory banks, a register and a controller. The register stores capacity information of each memory bank. The controller is connected to the register and memory banks and uses the capacity information to determine whether or not addresses are to be interleaved between a pair of memory banks. If the memory banks are of similar capacities, the addresses may be interleaved therebetween.

Abstract: A computer system executing virtual memory management and having a cache is operated in a manner to reduce cache misses by remapping pages of physical memory from which cache misses are detected. The method includes detecting cache misses, as by observing cache fill operations on the system bus, and then remapping the pages in the main memory which contain the addresses of the most frequent cache misses, so that memory references causing thrashing can then coexist in different pages of the cache. For a CPU executing a virtual memory operating system, a page of data or instructions can be moved to a different physical page frame but remain at the same virtual address, by simply updating the page-mapping tables to reflect the new physical location of the page, and copying the data from the old page frame to the new one.

Abstract: A method is provided for providing a cache architecture for a database system having a given number of request streams and a given number of pages of random access memory available for use in one or more caches. The cache architecture includes (i) an allocation of memory pages over a number of caches, and (ii) an assignment of the request streams to the caches. Given that the number of caches is less than the number of streams, the method according to the invention allocates memory pages to the caches and assigns streams to the caches so as to optimize the memory access hit ratio for a given trace of memory requests from the streams. The method includes obtaining characterization information for the request streams (mean burst sizes and cache depth distributions based on the sequence of requests in the trace), and using the characterization information to predict the hit ratios for proposed superpositions of the request streams.

Abstract: A hard disk format is disclosed which sequentially arranges a number of different sector types, each having a different format, into frames which are repeated around the tracks of a magnetic disk. The sector types and frame arrangements are chosen so that servo bursts are optimally located around the tracks of a magnetic disk. The sectors of the magnetic disk may have servo bursts located virtually anywhere within each sector. A magnetic disk controller used in conjunction with the magnetic disk processes each sector during reading from or writing to a sector according to whether or not the sector contains a servo burst.

Abstract: A cache bypass mechanism automatically avoids caching of data for instructions whose data references, for whatever reason, exhibit low cache hit ratio. The mechanism keeps a record of an instruction's behavior in the immediate past, and this record is used to decide whether its future references should be cached or not. If an instruction is experiencing bad cache hit ratio, it is marked as non-cacheable, and its data references are made to bypass the cache. This avoids the additional penalty of unnecessarily fetching the remaining words in the line, reduces the demand on the memory bandwidth, avoids flushing the cache of useful data and, in parallel processing environments, prevents line thrashing. The cache management scheme is automatic and requires no compiler or user intervention.

Abstract: A data processing system in which a plurality of processors or other memory access devices operate either synchronously or asynchronously with a memory interface device, which in turn provides access to one or more memory units on a time-division basis. This is accomplished by providing each memory unit a series of time-divisioned access opportunities and controlling the phase relationship between these time-divisioned access opportunities. Accordingly, two or more access devices can address an equal number of memory units simultaneously.

Abstract: A data memory system comprising a memory including a plurality of memory locations from which a stored data is readable and to which data is writable, an address latch for receiving and holding from an external device a relative address designating a memory location to be accessed, and an address decoder for designating an absolute address of a memory location of the plurality of memory locations on the basis of the relative address held in the address latch. This designated memory location is called an "m"th memory location. An address translation unit is controlled to change the "m"th memory location designated by the relative address to an "n"th memory location which is different from the "m"th memory location, where "m" and "n" are positive integers, based on the number of writes to the memory and the existence of coincident data in the "m"th and "n"th memory locations.

Abstract: A Write/Load cache protocol is described which may be used for maintaining cache coherency and performing barrier synchronization in multiprocessor computer systems, and for cooperating with prefetch mechanisms to allow data to be loaded into a central processor unit's (CPU) cache (in both single and multiprocessor systems) in anticipation of future memory references. The new protocol is defined such that when a cache observes a Write/Load command (and associated data item) on a bus to which the cache is attached, the cache is accessed and (a) if the data item is in the cache, the new value of the data item from the bus is copied into and replaces the data item in cache; and (b) if the data item is not in the cache, a new data item is created therein (preferably using the normal cache replacement policy), and the value of the data item on the bus is loaded into the cache. Thus, a protocol is provided which allows cache to be loaded via an external entity, i.e.

Abstract: A method for updating a LRU array in a cache having a RAM. The LRU array has a self-timing signal for the read operation of the LRU array, in conjunction with a cache RAM read cycle. According to the method, first, a cache RAM cycle is begun. Then, it is determined whether a hit condition exists with respect to a tag associated with the LRU array. A self-timing signal is generated if the hit condition exists. In response to the self-timing signal, and in the cache RAM read cycle, an LRU write operation is begun with respect to the LRU array. The LRU write operation includes the steps of providing a write signal to the LRU array, and of precharging the LRU array. The LRU write operation is extended for a time sufficient for the precharging of the LRU bit line to complete. This can result in the LRU write operation extending into the next cache cycle. Additionally, the LRU array may be provided with an LRU dummy cell.

Abstract: A cache memory stores data from a source. Each item of data is identified by an address having a plurality of bits divided into four groups. A multiplexer responds to a control signal by selectively applying two of the groups of bits to address inputs of a tag memory and a random access memory, and selectively applying the other two groups of bits to a data input of said tag memory. The multiplexer enables different groups of address bits to address the two memories. A comparator compares a first set of bits formed by the other two groups of address bits to a second set of bits read from said tag memory. A memory controller causes data to be read from the random access memory when the first and second sets of bits match. When the first and second sets of bits do not match, the memory controller causes data to be read from the source and stored in the random access memory. In the latter instance, the tag memory stores the bits present at its data input.

Abstract: A method for controlling access to a memory includes the step of defining a group of priority codes, each of which represents an order for granting simultaneous memory access requests. One of the group of priority codes is selectively provided to a memory controller. A request to access memory is then granted according to the selected priority code.

Abstract: A sequencer map is disclosed which combines a data field and a next-address field into a single field to thereby reduce the word length of instructions required to operate a magnetic disk drive. The combined data and next-address field has two different functions. In one mode, the combined data and next-address field contains a condition code and a next-address. The condition code identifies a condition and instructions to go to a next address in the sequencer map depending on whether the condition is met. In this mode, the next address to be carried out if the condition is met is contained in the combined data and next-address field. In a second mode, the combined data and next-address field is used to store information which is then output for comparison to information read from the disk, or for writing onto the disk during formatting, or which is not used.

Abstract: A computing system is presented which includes a memory, an input/output adapter and a processor. The processor includes a write back cache in which dirty data may be stored. When performing a coherent write from the input/output adapter to the memory, a block of data is written from the input/output adapter to a memory location within the memory. The block of data contains less data than a full cache line in the write back cache. The write back cache is searched to determine whether the write back cache contains data for the memory location. When the search determines that the write back cache contains data for the memory location a full cache line which contains the data for the memory location is purged.

Abstract: A dual port random access memory capable of inputting/outputting data bit by bit includes a plurality of memory cell arrays (100a, 100b, 100c, 100d) accessible in parallel, a plurality of data registers (9a, 9b, 9c, 9d) arranged to be connected to memory arrays, and transfer gates (8a', 8b', 8c', 8d') for selectively connecting each of the data registers to one memory array in response to a destination designating signal. The transfer gate includes elements (T1, T2) for connecting the data registers and the memory arrays such that each of the plurality of memory arrays is connected to different data registers. Each of the data registers is capable of transferring data of one row of the memory array at one time. The data register is capable of serially inputting and outputting data. This structure enables rearrangement of data and transfer of data row by row between memory arrays in the memory device.