Abstract: A graphics processor is described that includes a single instruction, multiple thread (SIMT) architecture including hardware multithreading. The multiprocessor can execute parallel threads of instructions associated with a command stream, where the multiprocessor includes a set of functional units to execute at least one of the parallel threads of the instructions. The set of functional units can include a mixed precision tensor processor to perform tensor computations to generate loss data. The loss data is stored as a first floating-point data type and scaled by a scaling factor to enable a data distribution of a gradient tensor generated based on the loss data to be represented by a second floating point data type.

Abstract: An arithmetic device and an electronic device having small power consumption is provided. An arithmetic device and an electronic device capable of high-speed operation is provided. An arithmetic device and an electronic device capable of suppressing heat generation is provided. The arithmetic device includes a first arithmetic portion and a second arithmetic portion. The first arithmetic portion includes a first CPU core and a second CPU core. The second arithmetic portion includes a first GPU core and a second GPU core. The CPU cores each have a power gating function and each include a first data retention circuit electrically connected to a flip-flop. The first GPU core includes a second data retention circuit capable of retaining an analog value and reading out the analog value as digital data of two or more bits. The second GPU core includes a third data retention circuit capable of retaining a digital value and reading out the digital value as digital data of one bit.

Abstract: One or more shader processor inputs (SPIs) provide work items from a thread group for execution on one or more shader engines. A command processor selectively dispatches the work items to the SPIs based on a size of the thread group and a format of cache lines of a cache implemented in the one or more shader engines. The command processor operates in a tile mode in which the command processor schedules the work items in multidimensional blocks that correspond to the format of the cache lines. In some cases, the format of the cache lines is determined by a texture surface format and a swizzle mode for storing texture data. The SPIs (or corresponding drivers) adaptively select wave size, tile size, and wave walk mode based on thread group size, UAV surface format. The SPIs adaptively launch and schedule waves in a thread group based on selected file size, wave walk mode, and wave size to improve cache locality, reduce memory access, and create address pattern to improve memory efficiency.

Abstract: A computer system stores information for a plurality of layouts of one or more user interface elements locally. Each layout corresponds to at least one type of display device, and includes one or more objects associated with the one or more user interface elements. Upon receiving a request for rendering a first user interface element on a display device, the computer system identifies a type of the display device and determines a first one of the at least one type of display device accordingly. The computer system then extracts information for a first layout corresponding to the first one of the at least one type of display device (e.g., information for a subset of objects that is stored with the first layout and corresponds to the first user interface element), and renders the subset of objects corresponding to the first user interface element on the display device accordingly.

Abstract: Systems, apparatuses and methods may provide for technology that sends a first message via an input output (IO) link, wherein the first message includes a first rendering asset and an identifier (ID) associated with the first rendering asset. The technology may also exclude a second rendering asset from a second message in response to the ID being shared by the first rendering asset and the second rendering asset and send the second message via the IO link, wherein the second message includes the ID. In one example, the ID is a hash ID.

Abstract: A system enabling a distributed 3D engine for performing dynamic load balancing through virtual worlds are provided. The system comprises one or more server computers comprising memory and at least one processor, the memory storing a data structure representing at least one portion of a virtual or real world as a plurality of cells storing virtual objects. The memory further stores a distributed 3D engine comprising a resource manager implemented in a distributed deployment and a plurality of individual software engines. Resources are dynamically allocated via the distributed deployment to one or more cells based on a current load and a corresponding computed and ranked demand. In some embodiments, the demand further considers one or more of an amount of virtual objects and level of interactions within the portion of the persistent virtual world system visible to a user avatar. Methods thereof are also provided.

Abstract: A method and system for generating attention pointers, including: displaying, in a display of a mobile device, an object within and outside a field of view (FOV) of an user wherein the object outside the FOV are real objects; monitoring, by a processor of the mobile device, for a change in the object within and outside the FOV; in response to a change, generating by the processor one or more attention pointers within the FOV of the user for directing user attention to the change in the object which is either inside or outside the FOV; and displaying, by the processor, on a virtual screen within the FOV to the user, the one or more attention pointers wherein the one or more attention pointers are dynamically configured to interact with the user in response to detections based on a movement of the user or the object within or outside the FOV of the user.

Abstract: A method of packing coverage in a graphics processing unit (GPU) may include receiving an indication for a portion of an image, determining, based on the indication, a packing technique for the portion of the image, and packing coverage for the portion of the image based on the packing technique. The indication may include one or more of: an importance, a quality, a level of interest, a level of detail, or a variable-rate shading (VRS) level. The indication may be received from an application. The packing technique may include array merging. The array merging may include quad merging. The packing technique may include pixel piling. The packing technique may be a first packing technique, and the method may further include determining, based on the indication, a second packing technique for the portion of the image, and packing coverage for the portion of the image based on the second packing technique.

Abstract: A method of simulating physics in a virtual worlds system includes: instantiating a multi-user virtual environment; selecting a plurality of physics hosts from a plurality of client devices based on predefined selection criteria; obtaining a request to modify an object within the multi-user virtual environment; in response to obtaining the request to modify the object, providing the request to the plurality of hosts and instructions to determine a candidate subsequent state of the object; obtaining a plurality of candidate subsequent states of the object, including a respective candidate subsequent state from each of the plurality of physics hosts; determining a subsequent state of the object based on the plurality of candidate subsequent states of the object; and providing the subsequent state of the object to the plurality of client devices and instructions to update their versions of the multi-user virtual environment based on the subsequent state of the object.

Abstract: A rendering system comprises a host device disposed in communication with one or more rendering pipelines. Each rendering pipeline comprises a rendering device and a display device. Each display device enables one or more users to view a scene rendered on the host device. Each rendering pipeline provides the user with independent control of their perspective of the scene. The host device receives a CG camera definition from each rendering pipeline and uses it to perform geometry culling and creates a z-buffer for each rendering pipeline. For each rendering pipeline, the rendering device receives a z-buffer and renders a frame buffer for the display device. This architecture reduces the rendering power requirements of the rendering device for each rendering pipeline as compared to performing all rendering on the rendering device, and is particularly useful when multiple users are viewing a complex scene such as a high fidelity simulation environment.

Abstract: A server that includes a graphics processing unit (GPU) may receive, from a first application that is remote from the server, a first request to reserve a first number of cores of the GPU for a first amount of time. The server may also receive, from a second application that is also remote from the server, a second request to reserve a second number of cores of the GPU for a second amount of time that at least partly overlaps the first amount of time. The server may determine that the first request is associated with a higher priority than the second request and, in response, may reserve the first number of cores for the first amount of time for the first application. The server may send, to the first application, an indication that the first number of cores have been reserved as requested by the first application.

Abstract: An example method of hardware-assisted graphics pipeline emulation comprises: computing, based on an input set of graphic primitives, a set of tessellation factors; computing, based on the input set of graphic primitives, a set of points specifying a plurality of patches; computing, based on the set of points, a tessellation count buffer; generating, based on the set of points and the tessellation count buffer, a tessellation offset buffer; performing, using the tessellation offset buffer, a tessellation setup stage; performing, by a graphics processing unit (GPU), a tessellation stage based on the set of tessellation factors, wherein the tessellation stage generates a plurality of output points corresponding to one or more patches of the plurality of patches; and computing, by a domain shader stage, a plurality of vertex positions defined by the plurality of output points.

Abstract: A rendering device signals a display device to capture and replay a current frame to maintain a static image while switching between multiple graphics processing units (GPUs) at a multiplexer (MUX). Replaying the current frame while the MUX switch is in progress smooths the user experience such that no screen blanking or artifacts are observable.

Abstract: Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially and distinctly packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.

Abstract: Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially and distinctly packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.

Abstract: A graphics pipeline of a graphics processing unit includes a compressor that receives one or more attributes (positional and non-positional) of a vertex that is output from a vertex shader. The compressor determines a format of the one or more attributes, and separates each attribute into parts based on the format of the attribute. The compressor compresses each respective part of the attribute based on a type of the part. The compressed parts of the attribute are stored in an attribute storage.

Abstract: A mechanism is described for facilitating inference coordination and processing utilization for machine learning. A method of embodiments, as described herein, includes limiting execution of workloads for the respective contexts of a plurality of contexts to a specified subset of a plurality of processing resources of a processing system according to physical resource slices of the processing system that are associated with the respective contexts of the plurality of contexts.

Abstract: A GPU includes shader cores and a shader warp packer unit. The shader warp packer unit may receive a first primitive associated with a first partially covered quad, and a second primitive associated with a second partially covered quad. The shader warp packer unit may determine that the first partially covered quad and the second partially covered quad have non-overlapping coverage. The shader warp packer unit may pack the first partially covered quad and the second partially covered quad into a packed quad. The shader warp packer unit may send the packed quad to the shader cores. The first partially covered quad and the second partially covered quad may be spatially disjoint from each other. The shader cores may receive and process the packed quad with no loss of information relative to the shader cores individually processing the first partially covered quad and the second partially covered quad.

Abstract: Systems and methods are configured to adjust the timing of rendered frame scanout in response to fluctuations in a variable frame rate at which source frames are rendered.

Abstract: The present disclosure describes systems, methods, and non-transitory computer readable media for detecting user interactions to edit a digital image from a client device and modify the digital image for the client device by using a web-based intermediary that modifies a latent vector of the digital image and an image modification neural network to generate a modified digital image from the modified latent vector. In response to user interaction to modify a digital image, for instance, the disclosed systems modify a latent vector extracted from the digital image to reflect the requested modification. The disclosed systems further use a latent vector stream renderer (as an intermediary device) to generate an image delta that indicates a difference between the digital image and the modified digital image. The disclosed systems then provide the image delta as part of a digital stream to a client device to quickly render the modified digital image.