Abstract: A structure including a plurality of dielectric regions is described. The structure can include a rivet cell. The rivet cell can include a set of stacked vias. The rivet cell can extend through a stress hotspot of the structure. A length of the rivet cell can thread through at least one dielectric region among the plurality of dielectric regions. The rivet cell can be among a number of rivet cells inserted in the stress hotspot. The stress hotspot can be among a plurality of stress hotspots across the structure. A length of the rivet cell can be based on a model of a relationship between the length of the rivet cell and an energy release rate of the structure. The rivet cell can thread through an interface between a first dielectric region and a second dielectric region having different dielectric constants.

Abstract: Systems and methods for performing depth-dependent oxidation modeling and depth-dependent etch modeling in a virtual fabrication environment are discussed. More particularly, a virtual fabrication environment models, as part of a process sequence, oxidant dispersion in a depth-dependent manner and simulates the subsequent oxidation reaction based on the determined oxidant thickness along an air/silicon interface. Further the virtual fabrication environment performs depth-dependent etch modeling as part of a process sequence to determine etchant concentration and simulate the etching of material along an air/material interface.

Abstract: A method for designing a power network is provided and includes: initializing via widths and power-trace widths; determining whether utilization rates of first, second and third routing tracks are respectively equal to first, second and third values; when said utilization rate of said first routing tracks is not equal to said first value, adjusting said distance between first and second power traces until said utilization rate thereof is equal to said first value; when said utilization rate of said second routing tracks is not equal to said second value, adjusting said distance between third and fourth power traces until said utilization rate thereof is equal to said second value; and when said utilization rate of said third routing tracks is not equal to said third value, adjusting said distance between fifth and sixth power traces until said utilization rate thereof is equal to said third value.

Abstract: The present disclosure relates to system(s) and method(s) for interactively controlling the course of a functional simulation of DUV/SUV. The system comprises a testbench and the DUV/SUV connected to the testbench. The testbench generates a set of input data/packets as a stimulus to be processed by the DUV/SUV. The set of input data/packets is generated to simulate and verify the DUV/SUV. Further, the testbench identifies a pre-defined event at runtime during the simulation. Upon identification of the event, the testbench is configured to pause the simulation and transmit a notification message to a user indicating the occurrence of the event. Further, the testbench waits for a pre-defined time interval to receive one or more user inputs. The testbench further generates new stimulus based on the one or more user inputs and resumes the paused simulation with the new stimulus, thereby controlling the course of the functional simulation.

Abstract: The present disclosure discloses a charging control system, which includes: a master device, including a first USB interface and a first charging management circuit; at least one slave device, including a second USB interface and a second charging management circuit; a gating control circuit, which is arranged in the master device or the slave device, wherein an input terminal of the gating control circuit is coupled to the first USB interface and the second USB interface, and an output terminal of the gating control circuit is coupled to the first charging management circuit and the second charging management circuit to select and control a charging USB interface of the first charging management circuit and a charging USB interface of the second charging management circuit. Through the above mentioned way, multiple charging modes of the master device and the slave device may be implemented without software support.

Abstract: In one implementation, a multilayered printed circuit board is configured to redirect current distribution. The current may be distributed by steering, blocking, or otherwise manipulating current flows. The multilayered printed circuit board includes at least one power plane layer. The power plane layer does not distribute current evenly. Instead, the power plane layer includes multiple patterns with different resistances. The patterns may include a hatching pattern, a grid pattern, a directional pattern, a slot, a void, or a continuous pattern. The pattern is a predetermined spatial variation such that current flows in a first area differently than current flows in a second area.

Abstract: A method includes: generating a design layout according to a circuit design by placing first and second components; identifying a first area and a second area between the first component and the second component; and determining a first cell configuration of the first component according to the first component and a second cell configuration of the second component according to the second component. The method further includes selecting a first cell comprising a first capacitor from a cell library, wherein the first cell has a third cell configuration identical to the first cell configuration; selecting a second cell comprising a second capacitor from the cell library, wherein the second cell has a fourth cell configuration identical to the second cell configuration; placing a first cell array formed of the first cell in the first area; and placing a second cell array formed of the second cell in the second area.

Abstract: A circuit includes a reference node configured to carry a reference voltage level, a first node configured to carry a signal having a first voltage level or the reference voltage level, a second node configured to carry a power supply voltage having a power supply voltage level in a power-on mode and the reference voltage level in a power-off mode, and a plurality of transistors coupled in series between the first node and the reference node. Each transistor of the plurality of transistors receives a corresponding control signal of a plurality of control signals, and each control signal has a first value based on the power supply voltage in the power-on mode and a second value based on the signal in the power-off mode.

Abstract: A computer implemented method for analyzing a timing of an integrated circuit, wherein an interconnection of a first net of the integrated circuit includes at least one conducting segment formed in a wiring layer or a via layer, includes obtaining a plurality of resistances and a plurality of capacitances, which correspond to each of the at least one conducting segment, based on a process variation, counting a number of layers in which the at least one conducting segments is formed, and calculating a corner resistance and a corner capacitance of the first net, based on the number of layers, the plurality of resistances, and the plurality of capacitances, wherein the counting of the number of layers includes calculating an effective number of layers based on a resistance variability and/or a capacitance variability of each of the layers.

Abstract: An establishing method for the timing model includes: identifying at least one first victim path which is a boundary path in a circuit block; determining whether to remove a first aggressor path corresponding to the first victim path according to a transmission delay on the first victim path; finding a plurality of high-fanout circuit devices with a fanout number greater than a preset value in the circuit block; determining whether to remove each of the high-fanout circuit devices according to a connection position of each of the high-fanout circuit devices; identifying a plurality of second victim paths corresponding to each of the high-fanout circuit devices, and determining whether to keep or remove a second aggressor path corresponding to each of the second victim paths according to a transmission delay of each of the second victim paths.

Abstract: An FPGA system includes: an FPGA configured such that a partial reconfiguration is executable; and an external storage medium that is positioned outside of the FPGA and stores configuration data that is readable by the FPGA. The external storage medium stores first configuration data indicating a configuration of a circuit that is not subject to the partial reconfiguration and a second configuration data indicating a configuration of a circuit that is subject to the partial reconfiguration. The first configuration data includes configuration data indicating a configuration of a reconfiguration activation circuit for reading the second configuration data from the external storage medium and deploying the configuration indicated by the second configuration data.

Abstract: A computing system can perform a layout-to-schematic process on a geometric layout design of an integrated circuit, which can generate a device-level layout design for the integrated circuit. The computing system also can perform a parasitic extraction process on the geometric layout design by utilizing the device-level layout design for the integrated circuit. The computing system implementing the parasitic extraction process can sub-divide a conductor in the device-level layout design into multiple sub-divided conductor portions based on conversion rules corresponding to the physical properties of layers for the integrated circuit described in a technology file. The computing system can generate a physical layout design of the integrated circuit from the device-level layout design having the sub-divided conductor portions based on the technology file.

Abstract: Machine assisted system and method for performing dynamic thermal management (DTM) analysis are described. In one embodiment, the method can include receiving a power profile associated with IP blocks in an integrated circuit (IC) system modeled by a Krylov reduced order model (ROM). The power profile can represent power consumption of each of the blocks based on a predefined operating scenario. The method can additionally include evaluating the temperature of each of the blocks of the IC system for the current time step based on the power profile and the Krylov ROM. The method can further include calculating new power values based on the current temperature field of each of the blocks of the IC system, wherein the power profile can be updated with the new power value for the temperature of each of the blocks of the IC system for the next time step.

Abstract: Methods for generation of shape data for a set of electronic designs include inputting a set of shape data, where the set of shape data represents a set of shapes for a device fabrication process. A convolutional neural network is used on the set of shape data to determine a set of generated shape data, where the convolutional neural network comprises a generator trained with a pre-determined set of discriminators. The set of generated shape data comprises a scanning electron microscope (SEM) image.

Abstract: Embodiments include simulating a design under test on an electronic device. Aspects include running a test program on the design under test and capturing inputs into the design under test. Aspects also include storing the inputs into the design under test in a storage device. Responsive to determining that an event has occurred during execution of the test program, aspects include halting the test program on the design under test. Aspects further include enabling a user via a user interface to determine a cause of the event by performing a simulation of the design under test using the inputs stored in the storage device.

Abstract: A computer-based high-level synthesis (HLS) technique for circuit implementation includes providing a library as a data structure, wherein the library includes a function configured to perform a vector operation using one or more vector(s). The library can include a software construct defining a variable number of elements included in the vector(s). The number of elements can be determined from a variable included in an HLS application that uses the library to perform the function. The variable can specify an arbitrary positive integer value. The method also can include generating a circuit design from the HLS application. The circuit design can implement the function in hardware to perform the vector operation in one clock cycle. A data type of each element of the vector(s) may be specified as a further software construct within the library and determined from a further variable of the HLS application.

Abstract: A system for implementing functional logics of a verification IP using a transaction level modeling (TLM) is provided. The system includes (A) a stimulus generator to initiate a transaction and transmit the transaction through a transaction level model interface, (B) a verification IP unit to receive and process the transaction and (C) a signal-level driver to toggle pins of the design under test (DUT) based on the processed transaction. The verification IP unit is configured to (a) divide functional logics of a verification IP unit into one or more finite state machines (FSMs) when a transaction is received from a stimulus generator, (b) define a set of state variables for each of the one or more FSMs, (c) implement a state class for each state of the one or more FSMs and (d) modify the functionality of the one or more FSMs.

Abstract: A method, system and computer program product for appending abstractions to a testbench used for verifying the design of an electronic circuit. According to an embodiment of the invention, a method comprises identifying a set L of one or more support properties l for a set P of one or more properties p for a given electronic circuit; computing a plurality of hardware signals s of the given electronic circuit; and creating a plurality of abstract signals ABS, including declaring a fresh abstract signal abs_s for each of the hardware signals s, and creating a fresh abstract signal abs_l for each of the support properties l of the set L; for each of the properties p of the set P, creating an abstract property version abs_p; and appending the abstract signals ABS and the abstract property abs_p to the testbench to form an appended testbench.

Abstract: An electromagnetic resonance-type wireless power transmitter according to one embodiment of the present invention may comprise: a power conversion unit including a converter capable of converting a voltage received from a power supply unit into a particular voltage; a power transmission unit including a wireless power transmission coil for receiving the particular voltage from the power conversion unit and wirelessly transmitting power, using a particular resonance frequency; a communication unit capable of performing data communication with a wireless power receiver; and a control unit for controlling the power conversion unit, the power transmission unit, and the communication unit, wherein the wireless power transmission coil may comprise an outer coil part having a first loop shape, and an inner coil part disposed within the first loop shape and having a second loop shape, the direction of a current flowing through the outer coil part may be opposite to that of a current flowing through the inner coil par

Abstract: An approach is described for a method, system, and product for deferred merge based method for graph based analysis to reduce pessimism. According to some embodiments, the approach includes receiving design data, static and/or statistical timing analysis data, identifying cells and interconnects for performing graph based worst case timing analysis where merger of signals is deferred based on one or more conditions to reduce pessimism, and generating results thereof. Other additional objects, features, and advantages of the invention are described in the detailed description, figures, and claims.