Abstract: A semiconductor device according to the present invention includes: a through via formed to penetrate a semiconductor substrate; first and second buffer circuits; a wiring forming layer formed in an upper layer of the semiconductor substrate; a connecting wiring portion formed in an upper portion of the through via assuming that a direction from the semiconductor substrate to the wiring forming layer is an upward direction, the connecting wiring portion being formed on a chip inner end face that faces the upper portion of the semiconductor substrate at an end face of the through via; a first path connecting the first buffer circuit and the through via; and a second path connecting the second buffer circuit and the through via. The first path and the second path are electrically connected through the connecting wiring portion.

Abstract: To increase the efficiency of electronic design automation, execute partition-aware global routing with track assignment on an electronic data structure including a small block floorplan of a putative integrated circuit design. The small block floorplan is virtually partitioned into a proposed large block floorplan with a plurality of inter-large-block boundaries of a plurality of large blocks. Based on results of the executing, determine locations, on the inter-large-block boundaries, of a plurality of required ports corresponding to routes identified in the routing, as well as required sizes of the ports. Generate a physical partitioning based on the inter-large-block boundaries; align the ports with the inter-large-block boundaries; and generate a hardware description language design structure encoding the physical partitioning.

Abstract: For each of a plurality of source-sink pairs, a corresponding interconnect layer is selected having a reach length which permits propagation of a required signal within a required sink cycle delay. For a first clock cycle, a movable region for a first latch is located as a first plurality of overlapped regions one reach length from a source and the required sink cycle delay number of reach lengths from each one of the sinks; and the first plurality of overlapped regions is represented as nodes on a first cycle level of a topology search graph. Analogous actions are carried out for a second clock cycle of the required sink cycle delay. A latch tree is created based on the topology search graph, wherein a required number of latches is minimized, and at each of the cycle levels, all sinks of source nodes selected at a previous level are covered.

Abstract: A method of determining electromigration (EM) compliance of a circuit is performed. The method includes providing a layout of the circuit, the layout comprising one or more metal lines, and changing a property of one or more of the one or more metal lines within one or more nets of a plurality of nets in the layout. Each of the nets includes a subset of the one or more metal lines. The method also includes determining one or more current values drawn only within the one or more nets and comparing the determined one or more current values drawn with corresponding threshold values. Based on the comparison, an indication is provided whether or not the layout is compliant. A pattern of the one or more metal lines in the compliant layout is transferred to a mask to be used in the manufacturing of the circuit on a substrate.

Abstract: A per-chip equivalent oxide thickness (EOT) circuit sensor resides in an integrated circuit. The per-chip EOT circuit sensor determines electrical characteristics of the integrated circuit. The measured electrical characteristics include leakage current. The determined electrical characteristics are used to determine physical attributes of the integrated circuit. The physical attributes, including EOT, are used in a reliability model to predict per-chip failure rate.

Abstract: A system for designing an integrated circuit having pre-layout RC information is disclosed. The system includes: at least one processor; and at least one memory including computer program code for one or more programs, the at least one memory and the computer program code configured to, with the at least one processor, cause the system to: generate current and voltage information for a schematic having device array layout constraint included; create interconnection topology patterns and realizing route for the schematic; generate RC information according to the route; and determine if the schematic having the device array layout constraint and the RC information included violates one or more of the system design rule constraints. An associated method and a computer readable medium are also disclosed.

Abstract: A method for adaptive error correction in quantum computing includes executing a calibration operation on a set of qubits, the calibration operation determining an initial state of a quantum processor. In an embodiment, the method includes estimating, responsive to determining an initial state of the quantum processor, a runtime duration for a quantum circuit design corresponding to a quantum algorithm, the quantum processor configured to execute the quantum circuit design. In an embodiment, the method includes computing an error scenario for the quantum circuit design. In an embodiment, the method includes selecting, using the error scenario and the initial state of the quantum processor, a quantum error correction approach for the quantum circuit design. In an embodiment, the method includes transforming the quantum algorithm into the quantum circuit design, the quantum circuit design including a set of quantum logic gates.

Abstract: Vacant areas of a layer of an integrated circuit design are filled with shapes connected to the appropriate nets.

Abstract: An integrated circuit including a first standard cell including, first transistors, the first transistors being first unfolded transistors, a first metal pin, a second metal pin, and a third metal pin on a first layer, the first metal pin and the second metal pin having a first minimum metal center-to-metal center pitch therebetween less than or equal to 80 nm, a fourth metal pin and a fifth metal pin at a second layer, the fourth metal pin and the fifth metal pin extending in a second direction, the second direction being perpendicular to the first direction, a first via between the first metal pin and the fourth metal pin, and a second via between the third metal pin and the fifth metal pin such that a first via center-to-via center space between the first via and the second via is greater than double the first minimum metal center-to-metal center pitch.

Abstract: The present invention relates to a wireless charging device including a communication signal compensator, a communication signal compensator comprises a power detector configured to detect a magnitude of a communication signal received through each of the plurality of antennas, and a control unit configured to acquire a communication signal having the greatest signal magnitude as the detection result, select an antenna corresponding to the communication signal having the greatest signal magnitude among the plurality of antennas, and transmit, to the coupling antenna, a switch control signal for controlling the switch to be connected to the selected antenna.

Abstract: A method of verifying an integrated circuit stack includes adding a dummy layer to a contact pad of a functional circuit, wherein a location of the dummy layer is determined based on a location of a contact pad of a connecting substrate. The method further includes converting the dummy layer location to the connecting substrate. The method further includes determining whether the dummy layer is aligned with the contact pad of the connecting substrate. The method further includes adjusting the dummy layer location in the functional circuit when the dummy layer location is misaligned with the contact pad of the connecting substrate.

Abstract: The optimization of circuit parameters of variational quantum algorithms is a challenge for the practical deployment of near-term quantum computing algorithms. Embodiments relate to a hybrid quantum-classical optimization methods. In a first stage, analytical tomography fittings are performed for a local cluster of circuit parameters via sampling of the observable objective function at quadrature points in the circuit parameters. Optimization may be used to determine the optimal circuit parameters within the cluster, with the other circuit parameters frozen. In a second stage, different clusters of circuit parameters are then optimized in “Jacobi sweeps,” leading to a monotonically convergent fixed-point procedure. In a third stage, the iterative history of the fixed-point Jacobi procedure may be used to accelerate the convergence by applying Anderson acceleration/Pulay's direct inversion of the iterative subspace (DIIS).

Abstract: A method of generating a plurality of photomasks includes generating a circuit graph. The circuit graph comprises a plurality of vertices and a plurality of edges. Each of the plurality of vertices is representative of one of a plurality of conductive lines. The plurality of edges are representative of a spacing between the conductive lines less than an acceptable minimum distance. Kn+1 graph comprising a first set of vertices selected from the plurality of vertices connected in series by a first set of edges selected from the plurality of edges and having at least one non-series edge connection between a first vertex and a second vertex selected from the first set of vertices is reduced by merging a third vertex into a fourth vertex selected from the first set of the plurality of vertices. An n-pattern conflict check is performed and the photomasks generated based on the result.

Abstract: Systems and methods for dynamically sizing inter-kernel communication channels implemented on an integrated circuit (IC) are provided. Implementation characteristics of the channels, predication, and kernel scheduling imbalances may factor into properly sizing the channels for self-synchronization, resulting in optimized steady-state throughput.

Abstract: Swap insertion in mapping logical qubits on a quantum circuit is performed by obtaining an operation sequence including a plurality of operations to be executed on a quantum circuit. The quantum circuit including a plurality of physical qubits and a plurality of couplings. Finding a blocking set of operations including leading unresolved operation in the operation sequence. Calculating a first coupling score for each coupling of the plurality of couplings based on total reduction of shortest path lengths of a plurality of unresolved operations of the plurality of operations Selecting a coupling based on the first coupling score of each coupling. Updating the blocking set by removing any leading unresolved operations from the blocking set that can be performed after swapping a pair of logical qubits stored in a pair of physical qubits connected by the selected coupling.

Abstract: For exceptional logic element management, a method encodes a logic design as a linear array that includes a plurality of logic states. Each logic state includes one or more binary output variables, one or more binary input variables, one or more minterms of the one or more binary input variables, one or more maxterms of the one or more minterms, one or more present state values, and one or more next state values. The method identifies an exceptional logic element, wherein the exceptional logic element comprises one or more of an exceptional logic state, an exceptional state transition, and an exceptional input combination. In addition, the code displays the plurality of logic states excluding the exceptional logic elements from display.

Abstract: A per-chip equivalent oxide thickness (EOT) circuit sensor resides in an integrated circuit. The per-chip EOT circuit sensor determines electrical characteristics of the integrated circuit. The measured electrical characteristics include leakage current. The determined electrical characteristics are used to determine physical attributes of the integrated circuit. The physical attributes, including EOT, are used in a reliability model to predict per-chip failure rate.

Abstract: For implementing a logic design, a method encodes a logic design as a linear array that includes a plurality of logic states. The method calculates a combination map for a state transition between a start state and an end state of the plurality of logic states using the linear array to reduce computational overhead. In addition, the method identifies undefined binary input variable transitions for the state transition on the combination map. The method resolves the undefined binary input variable transitions in the linear array. The method generates a final logic design comprising Boolean logic from the linear array with the resolved binary input variable transitions. The method implements the final logic design in hardware by generating semiconductor gates that implement the Boolean logic.

Abstract: A method includes assigning a first color group to a first routing track of the layout. The method further includes assigning a second color group to a second routing track of the layout. The method includes assigning the first color group to a third routing track of the layout, wherein the second routing track is between the first routing track and the third routing track. The method further includes assigning a first color from the first color group to a first conductive element along the first routing track. The method further includes assigning a second color from the first color group to a second conductive element along the first routing track. The method further includes assigning a third color from the second color group to a third conductive element on the second routing track, wherein the third color is different from each of the first color and the second color.

Abstract: A semiconductor device includes a first standard cell and a second standard cell. A single diffusion break region extending in a first direction is formed in the first standard cell, and a first edge region extending in the first direction and having a maximum cutting depth in a depth direction perpendicular to the first direction is in the first standard cell. A double diffusion break region extending in the first direction is formed in the second standard cell, and a second edge region extending in the first direction and having the maximum cutting depth in the depth direction is formed in the second standard cell.