Abstract: An integrated circuit is provided. The integrated circuit includes a metallization pattern, a dielectric layer, and plural memory devices. The metallization pattern has plural first conductive features and a second conductive feature. The dielectric layer is over the metallization pattern, in which the dielectric layer has a first portion over the first conductive features and a second portion over the second conductive feature. The memory devices are at least partially in the first portion of the dielectric layer and respectively connected with the first conductive features. The first portion of the dielectric layer has a plurality of side parts respectively surrounding the memory devices and an extending part connecting the side parts to each other, and a thickness of the second portion is greater than a thickness of the extending part of the first portion of the dielectric layer.

Abstract: An organic light emitting diode (OLED) display panel with a light field camera includes a glass covering plate, an OLED pixel layer, and image sensor. A gradient refractive index lens is formed on the glass covering plate. A refractive index of the gradient refractive index lens gradually varies from a center of the gradient refractive index lens to an outer periphery. The OLED pixel layer is disposed on a bottom surface of the glass covering plate and includes OLED pixel units. A micro lens array is embedded on the OLED pixel layer and includes gradient refractive index micro lenses. A refractive index of each gradient refractive index micro lens gradually varies from a center of the gradient refractive index micro lens to an outer periphery. The image sensor is disposed on a bottom surface of the OLED pixel layer. The light field camera can acquire clear images without focusing.

Abstract: A method to fabricate a resistive change element. The method may include forming a stack over a substrate. The stack may include a conductive material, a resistive change material, a first surface, and a second surfaces opposite the first surface. The method may further include depositing a first material over the stack such that the first material directly contacts at least one of the first surface and the second surface of the stack. The method may also include after depositing the first material, forming a second material over the first material and evaporating a portion of the first material through the second material to create a gap between the second material and the at least one of the first surface and the second surface of the stack.

Abstract: A photodetector sensor array device as usable for camera chips comprises upper and lower contact layers of n+ and p+ semiconductor material either side of a light absorbing region made of either one layer, or two oppositely doped layers, of semiconductor material. Insulating trenches of dielectric material extending through the layers to form the individual pixels. Respective contacts are connected to the upper and lower contact layers so that each pixel can be reverse biased or forward biased. In operation, the device is reset with a reverse bias, and then switched to forward bias for sensing. After switching, carriers generated in response to photon absorption accumulate in potential wells in the light absorbing region and so reduce the potential barriers to the contact layers, which causes current to start to flow between the contacts after a time delay which is inversely proportional to the incident light intensity.

Abstract: A method for manufacturing an SOI wafer by performing a sacrificial oxidation treatment and reducing a thickness of an SOI layer of the SOI wafer, in which: the SOI wafer on which the sacrificial oxidation treatment is performed has a film thickness distribution with a one-way sloping shape; a thermal oxidation in the sacrificial oxidation treatment is performed by combining a non-rotating oxidation and a rotating oxidation, using a vertical heat treatment furnace; whereby a thermal oxide film having an oxide film thickness distribution with a one-way sloping shape canceling the film thickness distribution with a one-way sloping shape of the SOI layer, is formed on a surface of the SOI layer; and by removing the formed thermal oxide film, an SOI wafer having an SOI layer whose film thickness distribution with a one-way sloping shape has been resolved is manufactured.

Abstract: A solid-state image sensor includes a pixel formed, upon forming a structure where a photoelectric conversion layer is laminated on a wiring layer constituting a pixel circuit, by forming at least the photoelectric conversion layer and a wiring layer bonding layer on a different substrate from a semiconductor substrate in which the wiring layer is formed, and by bonding the wiring layer bonding film of the different substrate and the wiring layer of the semiconductor substrate together.

Abstract: An integrated chip comprises a substrate, an isolation structure and a gate structure. The isolation structure comprises one or more dielectric materials within the substrate and has sidewalls defining an active region in the substrate. The active region has a channel region, a source region, and a drain region separated from the source region by the channel region along a first direction. The source, drain and channel regions respectively have first, second and third widths along a second direction perpendicular to the first direction. The third width is larger than the first and second widths. The gate structure comprises a first gate electrode region having a first composition of one or more materials and a second gate electrode region having a second composition of one or more materials different than the first composition of one or more materials.

Abstract: A component carrier includes a stack having at least one electrically insulating layer structure and a plurality of electrically conductive layer structures, and a component embedded in the stack and having an array of pads on a main surface of the component. A first electrically conductive connection structure of the electrically conductive layer structures electrically connects a first pad of the pads up to a first wiring plane, and a second electrically conductive connection structure of the electrically conductive layer structures electrically connects a second pad of the pads up to a second wiring plane being different from the first wiring plane.

Abstract: Techniques regarding parallel gradiometric SQUIDs and the manufacturing thereof are provided. For example, one or more embodiments described herein can comprise an apparatus, which can comprise a first pattern of superconducting material located on a substrate. Also, the apparatus can comprise a second pattern of superconducting material that can extend across the first pattern of superconducting material at a position. Further, the apparatus can comprise a Josephson junction located at the position, which can comprise an insulating barrier that can connect the first pattern of superconductor material and the second pattern of superconductor material.

Abstract: A semiconductor device including a first material layer adjacent to a second material layer, a first via passing through the first material layer and extending into the second material layer, and a second via extending into the first material layer, where along a common cross section parallel to an interface between the two material layers, the first via has a cross section larger than that of the second via.

Abstract: A semiconductor device and manufacturing method includes a well structure, a gate stack structure spaced apart from the well structure, the gate stack structure being disposed over the well structure, and a source contact structure facing a sidewall of the gate stack structure. The semiconductor device further includes a channel pattern having pillar parts penetrating the gate stack structure, a first connecting part extending along a bottom surface of the gate stack structure from the pillar parts, and a second connecting part extending from the first connecting part to contact a first surface of the source contact structure facing the well structure.

Abstract: A transfer method and a transfer device of micro LEDs are provided. By horizontally and vertically stretching a tensile substrate evenly to make horizontal distances and vertical distances between the adjacent micro LEDs achieve predetermined target values, and at last, bonding the micro LEDs spaced apart into the target values to an array substrate. The method does not need to manufacture a patterned mold or a patterned transfer head, and production period is reduced, and production cost is lowered, which effectively improves current transfer methods of the micro LEDs.

Abstract: A substrate treatment apparatus for treating a substrate, the substrate treatment apparatus includes: an apparatus main body configured to perform a predetermined treatment on the substrate; a casing configured to house a predetermined component therein and to be attachable to and detachable from an upper part of the apparatus main body; a casing side connection part provided at the casing and connected to the predetermined component; a main body side connection part provided at the upper part of the apparatus main body and configured to be fitted into the casing side connection part; a guide part provided at the upper part of the apparatus main body and configured to move the casing in one direction; and a connection assisting mechanism configured to fit the casing side connection part into the main body side connection part while moving the casing in the one direction.

Abstract: A method of controlling contamination of a vapor deposition apparatus includes: a wafer loading step of loading a wafer for contamination evaluation into a chamber of the vapor deposition apparatus; a heat treatment step of heat treating the wafer for contamination evaluation at a heat treatment temperature of 1190° C. or more at a hydrogen flow rate of 30 slm or less; a wafer unloading step of unloading the wafer for contamination evaluation from the inside of the chamber; and a wafer contamination evaluation step of evaluating a level of metal contamination of the wafer for contamination evaluation. In a method of producing an epitaxial wafer, epitaxial growth is performed using a vapor deposition apparatus whose contamination is controlled by the contamination controlling method.

Abstract: By introducing new concepts into a structure of a conventional organic semiconductor element and without using a conventional ultra thin film, an organic semiconductor element is provided which is more reliable and has higher yield. Further, efficiency is improved particularly in a photoelectronic device using an organic semiconductor. Between an anode and a cathode, there is provided an organic structure including alternately laminated organic thin film layer (functional organic thin film layer) realizing various functions by making an SCLC flow, and a conductive thin film layer (ohmic conductive thin film layer) imbued with a dark conductivity by doping it with an acceptor and a donor, or by the like method.

Abstract: A method of producing a semiconductor epitaxial wafer is provided. The method includes irradiating a surface of a semiconductor wafer with cluster ions to form a modified layer in a surface portion of the semiconductor wafer, in which the modified layer includes a constituent element of the cluster ions in solid solution. The method further includes forming an epitaxial layer on the modified layer of the semiconductor wafer. The irradiating is performed such that a portion of the modified layer in a thickness direction becomes an amorphous layer, and an average depth of an amorphous layer surface from a semiconductor wafer surface-side of the amorphous layer is at least 20 nm from the surface of the semiconductor wafer.

Abstract: A method includes forming a metal gate in a first inter-layer dielectric, performing a treatment on the metal gate and the first inter-layer dielectric, selectively growing a hard mask on the metal gate without growing the hard mask from the first inter-layer dielectric, depositing a second inter-layer dielectric over the hard mask and the first inter-layer dielectric, planarizing the second inter-layer dielectric and the hard mask, and forming a gate contact plug penetrating through the hard mask to electrically couple to the metal gate.

Abstract: The present invention relates to a display device comprising—a plurality of OLED pixels comprising at least two OLED pixels, the OLED pixels comprising an anode, a cathode, and a stack of organic layers, wherein the stack of organic layers—is arranged between and in contact with the cathode and the anode, and—comprises a first electron transport layer, a first hole transport layer, and a first light emitting layer provided between the first hole transport layer and the first electron transport layer, and—a driving circuit configured to separately driving the pixels of the plurality of OLED pixels, wherein, for the plurality of OLED pixels, the first hole transport layer is provided in the stack of organic layers as a common hole transport layer shared by the plurality of OLED pixels, and the first hole transport layer comprises (i) at least one first hole transport matrix compound consisting of covalently bound atoms and (ii) at least one electrical p-dopant selected from metal salts and from electrically neu

Abstract: A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion and a stopper layer disposed on a bottom surface of the recess portion; a semiconductor chip disposed in the recess portion; a resin layer disposed on an active surface of the semiconductor chip; an encapsulant covering at least portions of side surfaces of the semiconductor chip and the resin layer and filling at least portions of the recess portion; a first redistribution layer disposed on the resin layer and the encapsulant; first redistribution vias penetrating through the resin layer to fill via holes in the resin layer exposing at least portions of the connection pads and electrically connecting the connection pads and the first redistribution layer to each other; and a connection member disposed on the resin layer and the encapsulant and including one or more second redistribution layers.

Abstract: Certain embodiments involve processes or systems for creating various high-temperature superconductive structures or materials. For example, a method can involve depositing a first layer of boron and a second layer of un-doped amorphous carbon on a substrate. The un-doped amorphous carbon is ferromagnetic. The first layer of boron and the second layer of un-doped amorphous carbon are melted by a laser pulse to form a melted boron-doped amorphous carbon. The melted boron-doped amorphous carbon is quenched to create a quenched boron-doped amorphous carbon that is diamagnetic and superconducting. The quenched melted boron-doped amorphous carbon includes a mixture of sp3 bonded carbon atoms and sp2 bonded carbon atoms and a superconducting transition temperature of the quenched boron-doped amorphous carbon is much higher than diamond and increases based on a boron concentration. Undoped Q-carbon is ferromagnetic with Curie temperature above 500K.