Abstract: An airbridge implements connections on a superconducting chip. It comprises a strip of superconductive material between a first superconductive area and a second superconductive area. A first end of said strip comprises a first planar end portion attached to and parallel with said first superconductive area, and a second end of said strip comprises a respective second planar end portion. A middle portion is located between said first and second planar end portions, forming a bend away from a plane defined by the surfaces of the first and second superconductive areas. First and second separation lines separate the end portions from the middle portion. At least one of said first and second separation lines is directed otherwise than transversally across said strip.

Abstract: Methods and systems for depositing material, such as doped semiconductor material, are disclosed. An exemplary method includes providing a substrate, forming a first doped semiconductor layer overlying the substrate, and forming a second doped semiconductor layer overlying the first doped semiconductor layer, wherein the first doped semiconductor layer comprises a first dopant and a second dopant, and wherein the second doped semiconductor layer comprises the first dopant. Structures and devices formed using the methods and systems for performing the methods are also disclosed.

Abstract: A photodetector device comprising n-type and p-type light absorbing regions arranged to form a pn-junction and n+ and p+ contact regions connected to respective contacts. The light absorbing regions and the contact regions are arranged in a sequence n+ p n p+ so that, after a voltage applied between the n+ and p+ contacts is switched from a reverse bias to a forward bias, electrons and holes which are generated in the light absorbing regions in response to photon absorption drift towards the p+ and n+ contact regions respectively, which causes current to start to flow between the contacts after a time delay which is inversely proportional to the incident light intensity.

Abstract: A power electronic switching device has a substrate facing in a normal direction with a first and a second conductive track, and a power semiconductor component is arranged on the first conductive track by an electrically conductive connection. The power semiconductor component has a laterally surrounding edge and an edge region and a contact region on its first primary side facing away from the substrate, and with a three-dimensionally preformed insulation molding that has an overlap segment, a connection segment and an extension segment, wherein the overlap segment, starting from the edge partially overlaps the edge region of the power semiconductor component.

Abstract: Techniques for tight pitch patterning are provided. In one aspect, a patterning method includes: forming mandrels on a substrate; forming spacers that are undoped alongside the mandrels, wherein gaps are present between the spacers; filling the gaps with a sacrificial material having a dopant; forming a mask having an opening marking a cut region of at least one of the spacers; removing the sacrificial material from the cut region of the at least one spacer via the mask; removing the mask; performing an anneal to diffuse the dopant from the sacrificial material into the spacers to form doped spacers, wherein following the anneal the cut region of the at least one spacer remains undoped; removing the cut region of the at least one spacer selective to the doped spacers; and patterning features in the substrate using the doped spacers as a hardmask. A patterning structure is also provided.

Abstract: A device for applying underfill material into a space between a substrate and a semiconductor chip is provided. The device includes a frame housing configured to cover at least an outer edge area of the semiconductor chip that is bonded to the substrate. The device also includes a sealant attached to the frame housing and configured to contact the outer edge area of the semiconductor chip. The device also includes an outlet made on the frame housing for evacuating the space; and an inlet made on the frame housing for injecting the underfill material to the space.

Abstract: Disclosed are a method of manufacturing a microstructure array that includes preparing a mold having a concave micro pattern array in which a plurality of concave micro patterns are arranged, preparing a perovskite precursor solution including a perovskite precursor and a hydrophilic polymer, coating the perovskite precursor solution on a substrate, disposing the mold on the perovskite precursor solution to confine the perovskite precursor solution in the plurality of concave micro patterns, obtaining a composite of perovskite nanocrystals and the hydrophilic polymer from the perovskite precursor solution in the plurality of concave micro patterns, and, and removing the mold to form a microstructure array in which a plurality of microstructures including a composite of the perovskite nanocrystals and the hydrophilic polymer are arranged, a microstructure array, a micro light emitting diode including the same, and a manufacturing method thereof, and a display device.

Abstract: An integrated circuit package comprising one or more electronic component(s); and one or more substrate(s), including a first substrate and a second substrate, wherein said first substrate including a first cavity on a first surface of said first substrate and a second cavity on a second surface of said first substrate, said second substrate includes a third cavity on a first surface of said second substrate and a fourth cavity on a second surface of said second substrate, said first substrate and said second substrate are stacked and coupled, and said one or more electronic component(s) is/are disposed inside said first cavity of first substrate and said fourth cavity of second substrate.

Abstract: The invention provides a method for positioning a wafer and a semiconductor manufacturing apparatus, which are applied to thin film processes. The method includes: Step S1: Obtain the state distribution of the first surface of the first wafer after the thin film process is performed on the first wafer, wherein the first surface is the surface opposite to a surface that the thin film formed thereon in the thin film process; Step S2: Determine whether the first wafer is located at the ideal positioning center according to the state distribution of the first surface, when the first wafer is not located at the ideal positioning center, according to the state distribution of the first surface adjusts the positioning position of the second wafer to be subjected to the thin film process, so that the second wafer is positioned at the ideal positioning center during the thin film process.

Abstract: A substrate processing apparatus includes a base with a process-side surface and a substrate support arranged on the process-side surface and designed to carry a substrate at its periphery. The periphery, more specifically the plane defined by the periphery, is spaced apart from the process-side surface. The substrate processing apparatus also includes a radiation sensor adapted to measure electromagnetic radiation arranged on a side of a back-side surface of the base. A radiation channel is arranged between the radiation sensor and the periphery of the substrate support, more specifically between the radiation sensor and the plane defined by the periphery, wherein the radiation channel is at least partially permeable to electromagnetic radiation.

Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a first top electrode on the first MTJ and a second top electrode on the second MTJ, a passivation layer between the first MTJ and the second MTJ, and an ultra low-k (ULK) dielectric layer on and directly contacting the passivation layer and around the first MTJ and the second MTJ. Preferably, a top surface of the passivation layer includes a V-shape and a valley point of the V-shape is higher than a bottom surface of the first top electrode.

Abstract: A semiconductor wafer dicing process is disclosed for dicing a wafer into individual dies. Scribe lines are formed within a polymer coating to expose regions of wafer to form a pre-processed product. The pre-processed product within the chamber is plasma etched to remove the exposed regions of the wafer to separate the individual dies and form a processed product. A frame cover is then removed and the processed product, wafer frame and adhesive tape are exposed to an oxygen plasma within the chamber to partially remove an outermost region of the polymer coating, which is most heavily contaminated with fluorine, to leave a residual polymer coating on the individual dies and form a post-processed product. The residual polymer coating on the individual dies of the post-processed product is then removed.

Abstract: FinFET varactors having low threshold voltages and methods of making the same are disclosed herein. An exemplary FinFET varactor includes a fin and a gate structure disposed over a portion of the fin, such that the gate structure is disposed between a first source/drain feature and a second source/drain feature that include a first type dopant. The portion of the fin includes the first type dopant and a second type dopant. A dopant concentration of the first type dopant and a dopant concentration of the second type dopant vary from an interface between the fin and the gate structure to a first depth in the fin. The dopant concentration of the first type dopant is greater than the dopant concentration of the second type dopant from a second depth to a third depth in the fin, where the second depth and the third depth are less than the first depth.

Abstract: A semiconductor device and method of manufacture are provided. A source/drain region is formed next to a spacer, which is adjacent to a gate electrode. An implantation is performed through an implantation mask into the source/drain region as well as the first spacer, forming an implantation region within the spacer.

Abstract: Microelectronic devices with through-substrate interconnects and associated methods of manufacturing are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate carrying first and second metallization layers. The second metallization layer is spaced apart from the semiconductor substrate with the first metallization layer therebetween. The semiconductor device also includes a conductive interconnect extending at least partially through the semiconductor substrate. The first metallization layer is in electrical contact with the conductive interconnect via the second metallization layer.

Abstract: The present disclosure relates to a rapid thermal processing apparatus for rapid heat treatment of a substrate, and particularly, to increasing the accuracy in measuring the temperature of a substrate to be thermally processed by configuring a thermocouple for measuring the temperature of the substrate under the same conditions as the substrate to be thermally processed so as to be attached to and detached from the chamber, and the present disclosure provides a rapid thermal processing apparatus having a thermocouple installed to measure a temperature of a substrate to be thermally processed located inside a chamber, and the rapid thermal processing apparatus includes a mounting hole formed in the chamber, and a thermocouple kit inserted into and mounted to the mounting hole so that a bonding portion of a thermocouple wire is located at a thermocouple substrate extending into the chamber.

Abstract: According to one aspect of the technique, there is provided a method of manufacturing a semiconductor device, including checking a leak from a process furnace before a substrate is processed. The checking includes: (a) measuring, by a partial pressure sensor provided at an exhaust pipe, an oxygen partial pressure value of a residual oxygen after the process furnace is vacuum-exhausted; (b) comparing the oxygen partial pressure value measured by the partial pressure sensor with a threshold value; and (c) when the oxygen partial pressure value is higher than the threshold value in (b), performing at least one among: purging the process furnace and evacuating the process furnace.

Abstract: A semiconductor device and method of manufacture are provided. In an embodiment a first contact is formed to a source/drain region and a dielectric layer is formed over the first contact. An opening is formed to expose the first contact, and the opening is lined with a dielectric material. A second contact is formed in electrical contact with the first contact through the dielectric material.

Abstract: An inorganic light emitting diode in which at least one energy control layer including an organometallic compound interacting with a hydroxyquinoline moiety is disposed between an emitting material layer and at least one charge transfer layer and an inorganic light emitting device including the diode are disclosed. An exciton recombination zone is formed at the central region in the EML, and inorganic luminescent particles have minimal surface defects by introducing the energy control layer. The inorganic light emitting diode and the inorganic light emitting device can improve their color purity and luminous efficiency.

Abstract: A method and apparatus for reducing as-deposited and metastable defects relative to amorphous silicon (a-Si) thin films, its alloys and devices fabricated therefrom that include heating an earth shield positioned around a cathode in a parallel plate plasma chemical vapor deposition chamber to control a temperature of a showerhead in the deposition chamber in the range of 350° C. to 600° C. An anode in the deposition chamber is cooled to maintain a temperature in the range of 50° C. to 450° C. at the substrate that is positioned at the anode. In the apparatus, a heater is embedded within the earth shield and a cooling system is embedded within the anode.