Abstract: A multi-wafer deposition tool includes a vacuum enclosure including a platen laterally surrounding multiple wafer stages, a spindle-blade assembly including a spindle and multiple transfer blades attached to the spindle, and a controller configured to transfer wafers between the multiple wafer stages through rotation of the multiple transfer blades around a rotation axis pasting through the spindle. A chamber clean process may be performed while the transfer blades of the spindle-blade assembly are positioned over the multiple wafer stages. Alternatively or additionally, a deposition cycle may be performed while the transfer blades of the spindle-blade assembly are positioned between neighboring pairs of the wafer stages and while a purge gas that flows out of purge gas openings into spaces between the wafer stages.

Abstract: Textured optoelectronic devices and associated methods of manufacture are disclosed herein. In several embodiments, a method of manufacturing a solid state optoelectronic device can include forming a conductive transparent texturing material on a substrate. The method can further include forming a transparent conductive material on the texturing material. Upon heating the device, the texturing material causes the conductive material to grow a plurality of protuberances. The protuberances can improve current spreading and light extraction from the device.

Abstract: A process for transferring a thin layer consisting of a first material to a support substrate consisting of a second material having a different thermal expansion coefficient, comprises providing a donor substrate composed of an assembly of a thick layer formed of the first material and of a handle substrate having a thermal expansion coefficient similar to that of the support substrate, and the donor substrate having a main face on the side of the thick layer introducing light species into the thick layer to generate a plane of weakness therein and to define the thin layer between the plane of weakness and the main face of the donor substrate; assembling the main face of the donor substrate with a face of the support substrate; and detachment of the thin layer at the plane of weakness, the detachment comprising application of a heat treatment.

Abstract: The current disclosure describes a tunnel FET device including a P-I-N heterojunction structure. A high-K dielectric layer and a metal gate wrap around the intrinsic channel layer with an interlayer positioned between high-K dielectric layer and the intrinsic channel layer of the P-I-N heterojunction. The interlayer prevents charge carriers from reaching the interface with high-K dielectric layer under the trap-assisted tunneling effect and reduces OFF state leakage.

Abstract: A circuit die may include an outermost circuit layer having electrical transmission routing and an alignment target overlying the outermost circuit layer.

Abstract: In accordance with some embodiments, a method for processing semiconductor wafer is provided. The method includes connecting a drum which stores the chemical liquid with a testing pipe. The method also includes guiding the chemical liquid in the drum into the testing pipe. In addition, the method includes detecting a condition of the chemical liquid in the testing pipe. The method further includes determining if the condition of the chemical liquid is acceptable. When the condition of the chemical liquid is acceptable, supplying the chemical liquid to a processing tool at which the semiconductor wafer is processed.

Abstract: A semiconductor processing system includes a semiconductor processing chamber, a pump, an exhaust line in fluid communication with the chamber through the pump, and a steam generator and reactor. The steam generator and reactor has a process conduit with an inlet in line in the exhaust line for generating superheated steam and effecting transformations of chemicals in the exhaust fluid flowing in exhaust line into the inlet.

Abstract: On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.

Abstract: A substrate treatment apparatus according to an embodiment includes: a tank configured to store a liquid chemical with which a plurality of substrates are treated; a piping having an ejection port that ejects the liquid chemical or bubbles into the tank; a plurality of rods that support the plurality of substrates in the tank; and a converter that is provided in the plurality of rods or the tank and that converts vibration applied to each substrate by the liquid chemical or the bubbles ejected from the piping into rotation in one direction around a center of the substrate as a rotational axis.

Abstract: A method includes forming a reconstructed wafer including encapsulating a device die in an encapsulant, forming a dielectric layer over the device die and the encapsulant, forming a plurality of redistribution lines extending into the dielectric layer to electrically couple to the device die, and forming a metal ring in a common process for forming the plurality of redistribution lines. The metal ring encircles the plurality of redistribution lines, and the metal ring extends into scribe lines of the reconstructed wafer. A die-saw process is performed along scribe lines of the reconstructed wafer to separate a package from the reconstructed wafer. The package includes the device die and at least a portion of the metal ring.

Abstract: A semiconductor manufacturing apparatus according to the present embodiment includes a tank, a heater, a bubble supplier, a sensor and a controller. The tank stores a chemical solution for processing a substrate. The heater heats the chemical solution. The bubble supplier supplies bubbles to the chemical solution in the tank. The sensor detects at least one of a concentration of the chemical solution, a water concentration of the chemical solution, specific gravity of the chemical solution and a vapor concentration of a gas discharged from the tank. The controller controls the supply of bubbles by the bubble supplier based on a detection result of the sensor.

Abstract: Micro light emitting diode inspection and repairing equipment including a carrying stage, an optical inspection module and an injection device is provided. The optical inspection module is arranged corresponding to the carrying stage to capture image information and obtain a position coordinate from the image information. The injection device is adapted to move to a target position of the carrying stage according to the position coordinate. The injection device includes a tube and a nozzle. The tube includes a first portion and a second portion connected to the first portion. The extending direction of the first portion is different from the extending direction of the second portion. A fluid blows to the target position after passing through the tube and the nozzle. An inspection and repairing method adopting the micro light emitting diode inspection and repairing equipment is also provided.

Abstract: Photovoltaic devices having photoactive layers coupled to buffer layers are disclosed. Such devices may be transparent to visible light but absorb near-infrared light and/or ultraviolet light. The photovoltaic devices may include a p-phenylene layer that acts as a buffer layer. The photovoltaic devices may include one or more photoactive layers. The one or more photoactive layers may include a single planar heterojunction, a single bulk heterojunction (BHJ), or multiple stacked BHJs that have complementary absorption characteristics, among other possibilities.

Abstract: Exemplary substrate processing system may include a chamber body that defines a processing region. The systems may include a liner positioned atop the chamber body. The liner may include first disconnect members. The systems may include a faceplate that is positioned atop the liner. The systems may include a support disposed within the chamber body. The support may include a plate comprising a heater. The plate may include second disconnect members. The support may include a shaft coupled with the plate. The support may include a dynamic plate disposed about the shaft below the plate. The support may include metallic straps that couple the plate with the dynamic plate. The dynamic plate may include inner disconnect members and outer disconnect members. Inner disconnect members may be engageable with second disconnect members in a transfer position. Outer disconnect members may be engageable with first disconnect members in a process position.

Abstract: A molecular electronic device (10) includes a framework of polynucleotides (3), one or more molecular electronic components (4) and one or more electrical contacts (7). The molecular electronic components and the electrical contacts are each connected to the plurality of polynucleotides such that the molecular electronic components and the electrical contacts are located with respect to the framework and with respect to each other. This forms a coupling between the electrical contacts and the molecular electronic components.

Abstract: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate having a first surface and a second surface opposite from the first surface, and a die on the first surface of the package substrate. In an embodiment, the electronic package further comprises a socket interface on the second surface of the package substrate. In an embodiment, the socket interface comprises a first layer, wherein the first layer comprises a plurality of wells, a liquid metal within the plurality of wells, and a second layer over the plurality of wells.

Abstract: A method and system for doping semiconductor materials using microwave exposure. In some embodiments, the surface of a semiconductor substrate coated with a layer of dopant material is exposed to a beam of microwave radiation, with the frequency of the microwave radiation chosen to coincide with a microwave absorption resonance of the dopant. A gyrotron is a preferred source of monochromatic microwaves capable of delivering the appropriate the power density. Under this microwave exposure, the dopant heats up and diffuses into the semiconductor. Since only the dopant is selectively excited, the atoms of the crystal lattice remain cooler. Additional cooling can be provided by a flow of cooling gas onto the surface. When the electric field of the microwave exposure is high enough to overcome the potential barrier of interstitial diffusion within the crystal, the dopants migrate to vacancies in the crystal lattice, and the semiconductor material becomes activated.

Abstract: A method for producing in a roll-to-roll process modules of thin film photovoltaic cells in a substrate film, the modules including the substrate with a photovoltaic layer inbetween a lower and upper electrode layer, by using an apparatus including a belt conveyor, and scribe and print stations arranged at respective positions along a transport direction of the belt conveyor to create an interconnection structure between the photovoltaic cells including an arrangement of structural elements having one or more conductive and isolating scribe lines and a conductive body connecting adjacent thin film photovoltaic cells.

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate, a first inter-level dielectric (ILD) layer above the substrate, and a second ILD layer above the first ILD layer. A first capacitor and a second capacitor are formed within the first ILD layer and the second ILD layer. A first top plate of the first capacitor and a second top plate of the second capacitor are formed at a boundary between the first ILD layer and the second ILD layer. The first capacitor and the second capacitor are separated by a dielectric area in the first ILD layer. The dielectric area includes a first dielectric area that is coplanar with the first top plate or the second top plate, and a second dielectric area above the first dielectric area and to separate the first top plate and the second top plate. Other embodiments may be described and/or claimed.

Abstract: The instant disclosure includes an alignment system. The alignment system includes a first set of alignment marks, a second set of alignment marks, and a third set of alignment marks. The first, second and third alignment marks correspondingly includes a plurality of segments separated into groups. Each of the group being symmetric to a respective other group. The third set of alignment marks are diagonal to the first set of alignment marks and the second set of alignment marks.