Abstract: A hybrid quantum-classical (HQC) computer takes advantage of the available quantum coherence to maximally enhance the power of sampling on noisy quantum devices, reducing measurement number and runtime compared to VQE. The HQC computer derives inspiration from quantum metrology, phase estimation, and the more recent “alpha-VQE” proposal, arriving at a general formulation that is robust to error and does not require ancilla qubits. The HQC computer uses the “engineered likelihood function” (ELF) to carry out Bayesian inference. The ELF formalism enhances the quantum advantage in sampling as the physical hardware transitions from the regime of noisy intermediate-scale quantum computers into that of quantum error corrected ones. This technique speeds up a central component of many quantum algorithms, with applications including chemistry, materials, finance, and beyond.

Abstract: A method of operating a storage device includes sensing a standby current flowing through the storage device, determining based on the sensed standby current and at least one reference value whether a product abnormality has occurred within the storage device, and when it is determined the product abnormality has occurred, performing a step-wise control operation in which two or more control processes associated with an operation of the storage device are sequentially executed.

Abstract: A storage device configured for hardware verification is disclosed. The storage device comprises a first hardware component comprising a connector and a first verification logic. The first validation logic is configured to detect a criterion and generate a first signal via the connector in response to detecting the criterion. The storage device also comprises a second hardware component coupled to the first hardware component via the connector. The second hardware component comprises a second validation logic, where the second validation logic is configured to monitor and receive the first signal via the connector. In response to receiving the first signal, the second validation logic is configured to compare the received first signal to an expected signal and generate a result. The storage device is configured to take an action in response to the result.

Abstract: Techniques regarding the development and/or analysis of one or more quantum computing programs are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise a circuit component, operatively coupled to the processor, that can create a quantum computing program over a period of time. The computer executable components can also comprise a visualization component, operatively coupled to the processor, that can generates a quantum state visualization that depicts a characterization of the quantum computing program over the period of time.

Abstract: A method for validation and runtime estimation of a quantum algorithm includes receiving a quantum algorithm and simulating the quantum algorithm, the quantum algorithm forming a set of quantum gates. The method further includes analyzing a first set of parameters of the set of quantum gates and analyzing a second set of parameters of a set of qubits performing the set of quantum gates. The method further includes transforming, in response to determining at least one of the first set of parameters or the second set of parameters meets an acceptability criterion, the quantum algorithm into a second set of quantum gates.

Abstract: Embodiments of the disclosed technology concern transforming a high-level quantum-computer program to one or more symbolic expressions. Because the transformations lead to symbolic expressions in the compiled code, one can extract these to arrive at symbolic resource estimates for the quantum program. In cases where these transformations do not yield closed-form solutions, they can still be evaluated many orders of magnitude faster than it was possible using other resource estimation tools. Having access to such symbolic or near-symbolic expressions not only greatly improves the performance of accuracy management and resource estimation, but also better informs quantum software developers of the bottlenecks that may be present in the quantum program. In turn, the underlying quantum-computer program can be improved as appropriate.

Abstract: Systems and methods are disclosed for checker cores for fault tolerant processing. For example, an integrated circuit (e.g., a processor) for executing instructions includes a processor core configured to execute instructions of an instruction set; an outer memory system configured to store instructions and data; and a checker core configured to receive committed instruction packets from the processor core and check the committed instruction packets for errors, wherein the checker core is configured to utilize a memory pathway of the processor core to access the outer memory system by receiving instructions and data read from the outer memory system as portions of committed instruction packets from the processor core. For example, data flow from the processor core to the checker core may be limited to committed instruction packets received via dedicated a wire bundle.

Abstract: A method and apparatus are disclosed for efficient hybrid automatic repeat request (HARQ) process utilization for semi-persistent and dynamic data transmissions, wherein a reserved HARQ process identification (ID) can be reused. A subset of a plurality of HARQ process IDs is reserved to use for a semi-persistent allocation, and data is transmitted based on the semi-persistent allocation. A dynamic allocation is received via a physical downlink control channel (PDCCH). At least one of the reserved HARQ process IDs is selectively used for transmitting data based on the dynamic allocation.

Abstract: A system-on-chip includes a memory, an error injection controller, an injection logic circuit, and an error detection circuit. The error injection controller is configured to generate and transmit error data, and at least one of read and write access requests associated with the memory to the injection logic circuit. The injection logic circuit is configured to access the memory based on at least one of the read and write access requests to execute at least one of read and write operations. The injection logic circuit is further configured to inject an error in at least one of first data and second data to generate at least one of erroneous first data and erroneous second data, respectively. The error detection circuit is configured to detect an error in at least one of the erroneous first data and the erroneous second data to generate an error signal.

Abstract: A method begins by a load balancing module of a distributed storage network (DSN) determining availability of a plurality of DSN processing units of a set of DSN processing units based on availability information associated with the plurality of DSN processing units and in response to determined availability, selecting a DSN processing unit form the set to process a data access request. The method continues with the load balancing module receiving an indication that the DSN processing unit is no longer available from the DSN processing unit while the DSN processing unit continues to process previously pending data access requests. The method continues with the load balancing module cancelling selection of the DSN processing unit to process the data access request; and receiving a second indication from the DSN processing unit indication that the DSN processing unit is available.

Abstract: A control method for an optical transceiver includes interrupting internal repetitive internal processing in response to a command from a host apparatus and executing an interrupt process for transmitting monitoring data. The method sets a processing mode of the interrupt process to a first processing mode when a processing time necessary to execute the interrupt process and one cycle of the repetitive processing is shorter than a threshold value, and to a second processing mode when the processing time necessary to execute the interrupt process and one cycle of the repetitive processing is longer than the threshold value. In the first mode, the interrupt process stores first monitoring data read out from a memory unit in a transmission register, stops the stretching of a clock signal, and subsequently reads out second monitoring data from the memory unit to follow the first monitoring data.

Abstract: The present technology includes a test system. The test system includes a memory device configured to store an initial setting value for performing normal operations, and a test device configured to generate an operation command set including a test value that is a result of a test operation of the memory device, and configured to transmit the operation command set to the memory device. The memory device performs an operation by using the test value based on the operation command set, replaces the initial setting value with an operation value that is generated as a result of the operation, and stores the operation value.

Abstract: Disclosed is a capability test method based on a joint test support platform. The method includes steps of describing an initial capability in a test, combining a capability to be developed based on the initial capability, and determining an evaluation strategy and a joint task background information of the test. Further, the method includes generating a logical shooting range for the joint test support platform according to the joint task background information, developing a test scenario according to the joint task background information and the logical shooting range, decomposing the test scenario, determining a test plan corresponding to the test scenario, executing the test according to the test plan, analyzing and evaluating a test result of the test, and generating one or more joint capability evaluation reports for the test.

Abstract: Technology for error correcting data stored in memory dies is disclosed. Codewords, which may contain data bits and parity bits, are stored on a memory die. The memory die is bonded to a control die through bond pads that allow communication between the memory die and the control die. The codewords are decoded at the control die based on the parity bits. If the control die successfully decodes a codeword, the control die may send the data bits but not the parity bits to a memory controller. By not sending the parity bits to the memory controller, substantial bandwidth is saved. Also, substantial power may be saved. For example, the interface between the control die and the memory controller could be a high speed interface.

Abstract: An electronic device includes a cache with a cache controller and a cache memory. The electronic device also includes a cache policy manager. The cache policy manager causes the cache controller to use two or more cache policies for cache operations in each of multiple test regions in the cache memory, with different configuration values for the two or more cache policies being used in each test region. The cache policy manager selects a selected configuration value for at least one cache policy of the two or more cache policies based on performance metrics for cache operations while using the different configuration values for the two or more cache policies in the test regions. The cache policy manager causes the cache controller to use the selected configuration value when using the at least one cache policy for cache operations in a main region of the cache memory.

Abstract: A memory device includes a memory component that stores data. The memory device also includes a processor that receives a signal indicating that the memory component is coupled to the processor and retrieves information from the memory component. The information may include one or more algorithms capable of being performed by the memory component. The processor may then receive one or more packets associated with one or more data operations regarding the memory component. The processor may then perform the one or more data operations by using the memory component to employ the one or more algorithms.

Abstract: A data storage device may include a storage and a controller. The storage configured to store data. The controller configured to perform a normal read operation based on a default read voltage in accordance with a read request of a host device and to perform a read retry operation using at least one retry read voltage when the normal read operation fails. The controller may comprises a hit ratio table configured to store read success records as hit ratios of retry read voltages in association with workloads, each workload being associated with a set of retry read voltages, and a read voltage determiner configured to determine the workload when the normal read operation fails and to select the set of retry read voltages associated with the determined workload, the retry read voltages in the selected set being ordered from a highest hit ratio to a lowest hit ratio.

Abstract: A system is provided to receive a first request to write data to a storage system, which comprises an MRAM, a NOR, a DRAM, and a NAND. The system writes the data to the MRAM. The system copies the data from the MRAM: to the NOR in response to determining that the data is read at a frequency greater than a first predetermined threshold and is updated at a frequency less than a second predetermined threshold; to the DRAM in response to determining that the data is read at a frequency less than the first predetermined threshold and is updated at a frequency greater than the second predetermined threshold; and to the NAND in response to determining that the data is read at a frequency less than the first predetermined threshold and is updated at a frequency less than the second predetermined threshold.

Abstract: The present disclosure includes apparatuses and methods for ECC operation associated with memory. One example apparatus comprises a controller configured to perform an error correction code (ECC) operation on a codeword stored in the memory, wherein the codeword includes a first number of ECC bits and the first number of ECC bits are generated based on an encoding matrix, wherein each row of the encoding matrix has an odd number of bits having a binary value of 1.

Abstract: A memory system includes a storage medium including a target memory region having a plurality of memory units; and a controller configured to store data into one or more target memory units, each of which is estimated to take less time to perform a write operation thereon than any of the other memory units among the plurality of memory units, when performing a memory dump operation due to a sudden power off.