Abstract: An apparatus for the display and storage of television picture information by using a dynamic random access memory accessible from a computer. The apparatus includes an interface providing connection to the computer, an address modifying circuit, an address switching unit including a first input group connected to predetermined address lines of the address bus of the address generator and a second group connected to predetermined address lines of the interface, and a parallel to series converter. The inputs of the address modifying circuit being coupled to the output of the address switching unit to provide modified addresses for the memory when any of the input groups addresses the memory. The control inputs of the address switching unit and of the data switching unit are connected to a horizontal address line of the address bus associated with a horizontal address bit (X.sub.3) of low significance.

Abstract: An apparatus for storing and retrieving data in predetermined multi-bit length quantities containing fewer bits of data than word length quantities, including a memory for storing word length quantities at particular storage sites, a first buffer for selectively receiving data bits contained in a first predetermined portion of a word length quantity of data stored at a particular address within the memory, a second buffer for selectively receiving data bits contained in a second predetermined portion of the word length quantity of data stored at the particular address, a third buffer for alternatively receiving data bits contained in the second predetermined portion of the word length quantity of data stored at the particular address, a data bit generator for generating a null signal in the form of a predetermined number of data bits, a data bus having a first data transfer part and a second data transfer part connected to the memory, a CPU for causing the respective first and second portions of data and the

Abstract: Disclosed herein is a sequence controller wherein predetermined sequence processing can be executed by a built-in processor (2) in accordance with data transferred periodically from a processor (1) in a numerical control device (NC). The NC processor generates an interrupt signal (e) each time a transfer of data is completed. On the basis of the interrupt signal, the built-in processor in the sequence controller starts the predetermined sequence processing.

Abstract: Computer control memory apparatus is disclosed wherein the microinstructions may selectively have a variable bit length. A main control memory stores microinstructions having a basic length and they are read out and stored in a microinstruction register. Microinstruction prefixes are obtained from more than one source and are selectively added to the basic length microinstruction in the microinstruction register to create longer microinstructions, as needed, for controlling the operation of the computer. The microinstruction prefixes may be obtained from a secondary control memory that is addressed at the same time as the main control memory, or may be obtained from a field of N bits which is a part of a previous microinstruction read out of the main control memory and saved in an expansion register, or may be all zeroes when it is not desired to expand a microinstruction of basic length read out of the main control memory.

Abstract: A high speed multiplexed digital correlator device for correlating serial data against reference data. The device includes a plurality of digital correlators configured to operate in parallel with their operations overlapping in time. The serial data is divided between the plurality of correlators by multiplexing means. The outputs of the plurality of correlators are summed to produce an overall correlation output signal. Due to the multiplexed configuration, the individual correlators operate at a much lower rate than the data rate of the serial data to be correlated. Also disclosed are synchronized mutliplexed correlators including multiple multiplexed correlators for correlating serial data differing in phase relationship with the reference data against which it is to be correlated.

Abstract: A method for compacting blocks of memory in a demand paged virtual address space which includes a plurality of virtual address pages includes identifying active and stable blocks to be compacted by defining a pointer to indicate a page of the virtual memory space, and advancing the pointer to continually indicate the page of the beginning of the available virtual memory space. As new blocks are allocated, they are located in the virtual address space beginning at the next available location of the advancing pointer. As blocks are referenced by the user, they are moved to the current location of the advancing pointer, so that, stable blocks may be collected together on stable pages and active blocks are collected together on active pages. A disk memory is provided, and periodically the pages containing collected stable blocks are "paged-out" to it.

Abstract: An electronic calculator includes a mode selection key and a memo mode selection key. The mode selection key is actuated to select a memo mode for inputting and printing out memo data and a calculation mode for operating arithmetic calculation. The memo mode selection key is actuated to absolutely select the memo mode during the calculation mode. Once the memo mode selection key is actuated and a print key is actuated to print out the memo data, the calculation mode is reselected, automatically, so that the calculator can continue to calculate.

Abstract: In a processor system having a central processor and secondary support processor mounted on a backplane board, a separate peripheral interrupt bus is provided for each secondary support processor to give full interrupt priority capability to peripheral devices connected to the support processors. The support processors (110, 120) and certain of the system's peripheral interface circuits (102, 104) are connected to the system's central processor (101) via a primary interrupt bus (105) and other peripheral interface circuits (112, 114, 122) are connected to their associated secondary processors (110, 120) via separate interrupt buses (115, 125) all on the same backplane board. The backplane board is divided into an upper section and a lower section and the primary interrupt bus and the interrupt request and acknowledge terminal pins for all circuit boards are in the lower section.

Abstract: An address translation system is provided which has a real storage, a virtual storage having a "V.dbd.R" segment (first segment), second segments to be subjected to two-level paging, and page table segments (third segments) to be used as a page table corresponding to the second segments, a segment table, a first page table which corresponds to the second segments, a second page table which corresponds to the page table segments, and a memory control unit having a virtual address register and a microprocessor for translating the virtual address in the virtual address register into a real address.

Abstract: Apparatus for maintaining duplicate copies of information stored in fault-tolerant computer main memories is disclosed. A non write-through cache memory associated with each of the system's processing elements stores computations generated by that processing element. At a context switch, the stored information is sequentially written to two separate main memory units. A separate status area in main memory is updated by the processing element both before and after each writing operation so that a fault occurring during data processing or during any storage operation leaves the system with sufficient information to be able to reconstruct the data without loss of integrity.To efficiently transfer information between the cache memory and the system main memories without consuming a large amount of processing time at context switches, a block status memory associated with the cache memory contains an entry for each data block in the cache memory.

Abstract: A data management apparatus includes a scanner for reading a plurality of pieces of image information, an optical disk for storing a plurality of pieces of image information read by the scanner, a keyboard for entering attribute names featuring the respective pieces of image information stored in the optical disk, a magnetic disk for storing classification names having higher correlation with the attribute names, and a display. The attribute name entered at the keyboard is used as a parameter to access the magnetic disk to retrieve the classification name having the highest similarity. This classification name is displayed on the display.

Abstract: The topography of a CMOS microprocessor chip includes address buffer circuitry along the bottom and lower left hand edges of the chip, data bus buffers disposed along the lower right hand edge of the chip, address register circuitry and an arithmetic logic unit contained in a register section adjacent to both the address buffer circuitry and data bus buffer circuitry, register transfer circuitry adjacent to and above the register section, P channel circuitry disposed directly above the register transfer circuitry for producing sum-of-minterm signals applied to the register transfer circuitry in response to the minterm signals produced by N channel circuitry disposed adjacent to and immediately above the P channel circuitry. Status register circuitry responsive to status register control logic disposed along the top edge of the chip is positioned in the register section for direct, low capacitance connection to the internal data bus.

Abstract: A portable electrocardiogram storing apparatus has an electrocardiogram amplifier, an A/D converter for sampling the amplifier output and converting it into a digital signal, a patient actuatable switch, a plurality of electrocardiogram memories, and means for selecting one of the memories for storing the digital signal when the switch is actuated. A time memory is also provided for storing a time when the apparatus is set, and a timer measures a lapse time after the setting. A selected electrocardiogram memory also stores the content of the timer at the time a respective digital signal is stored therein.

Abstract: In providing digital filters for remote control receivers, in particular, for audio-frequency centralized ripple control receivers in an economic manner, it is advantageous to be able to use a processor unit with as low a bit number as possible (for example, an 8-bit microcomputer). In a conventional design of a filter according to the prior art, the dynamic range which is provided with an 8-bit processor element is insufficient in ensuring a perfect operation of the filter when a quality factor Q of about 30 is needed for the intended purpose of use and, on the other hand, when the dynamic range of the wanted signal which is given in practice is taken into consideration. A solution is indicated which overcomes these difficulties, which particularly involves the selected arrangement of zeros in the pass-band of the filter.

Abstract: A controller for interfacing a single-chip microcomputer with external dynamic random-access memory, includes a subcircuit for generating a column-address strobe at a time after a row-address strobe is generated, and also includes a multiplexing subcircuit for providing the proper 8-bit portion of a 16-bit address output from the microprocessor to the 8-bit dynamic memory inputs, prior to receipt of the associated row-address or column-address strobe. The microprocessor utilizes the strobe-generation and multiplexing subcircuits to burst-refresh the dynamic memory, in one presently preferred embodiment. In another presently preferred embodiment, lines from an additional microprocessor output port are utilized with a resettable binary counter and a multiplicity of buffers, to count through the range of row addresses in cyclic fashion, with each address being incremented after the previously-addressed row of memory cells has been refreshed.

Abstract: In a floating-point arithmetic operation system performing an arithmetic operation on two given operands X, Y and providing the result Z of the arithmetic operation, the operands X and Y are each classified according to their attributes; and, at least part of the bits of the operand X, at least part of the bits of the operand Y or a predetermined set of bits are adopted as at least part of the result Z of the operation when the results of the classifications are one of predetermined combinations.

Abstract: Circuitry for automatically configuring the operating system software of a computer is disclosed. The circuitry includes a revision port which generates a unique eight-bit code indicating the latest revision level of the main circuit board in the computer. Each time revisions are made in the board during manufacturing or each time a circuit board containing new revisions is put into the system by maintenance or service personnel, the eight-bit code generated by the port is changed. During the process of configuring the operating system software, the central processing unit reads the code generated by the port and uses the revision information to load and link software routines which will operate properly with the revised circuitry.

Abstract: An improved chip topography for a disk memory controller circuit is provided which includes chip buffer circuitry disposed around the periphery of the chip wherein the chip buffer circuitry forms a quadrilateral outer framework on the chip and data I/O buffer circuitry forms a first side of the quadrilateral outer framework; data I/O buffer control circuitry disposed between first and second corners of the chip buffer circuitry and adjacent to the data I/O buffer circuitry; a microcontroller for regulating the functions of the disk memory controller chip wherein a first portion of the microcontroller is disposed adjacent to the data I/O buffer control circuitry and along a part of a second side of the chip buffer circuitry; drive control and unit select registers coupled to the microcontroller and the chip buffer circuitry, and disposed adjacent to the first portion of the microcontroller and along part of a third side and within a third corner of the chip buffer circuitry, said microcontroller further compri

Abstract: An interface unit for connecting a transmitting unit to a receiving unit, the transmitting being capable of transmitting data at a speed greater than the processing speed of the receiving unit. The interface includes a serially connected multistage register which receives input data from the transmitting unit at its input stage and reads out data stored in its output stage to the receiving unit. It also includes a control circuit and a counter storing a count corresponding to the quantity of data stored in the register, the counter being incremented by one each time data is added to the register and decremented by one each time data is read from the register output stage. The control circuit is composed of a decoder and write control circuit. The decoder provides a signal to the write control circuit indicative of the count in the counter. When a datum is to be received from the transmitting unit, it signals the interface through a gate circuit, this signal incrementing the memory.

Abstract: In an n-wide (n nominally equals 4) snapshot priority network apparatus the access of n+1 requestors to a memory unit is prioritized. Two requestors--the lowest priority one of normal system requestors called instruction processors plus a maintenance exerciser type requestor--share a single memory port which is nominally the lowest priority one of n such prioritized ports. Requests from both requestors are both honored upon a single priority snap, the instruction processor request nominally proceeding before the maintenance processor request. Although the n-wide priority network remains generally faster than any (n+1)-wide priority network, the maintenance exerciser type requestor is expediently serviced and cannot be locked out of access to memory by the competing higher priority requests of the instruction processor.