Abstract: A large capacity (8 memory banks of 524K error-corrected 36 bit words stored) high performance (latency as low as 240 nanoseconds, 12.8 gigabits/second aggregate data transfer capability with up to 11.4 gigabits/second utilized) pipelined (8 deep request pipeline) random access memory store simultaneously (to the limit of bank addressing conflicts) services intermixed requests from an internal exerciser plus ported requestors (up to 10) of plural types (3 types), which requestors are not of the same interface cycle time (30 nsec vs. 60 nsec). Furthermore, to such nonuniform interface cycle times, the bit-width of the data transfer interfaces (ports) to the requestors of plural types is also not uniform, but is actually wider (4 interface words of 36 bits each=144 bits) to faster (30 nanosecond) requestors than is that data transfer bit-width (2 interface words=72 bits) to slower (60 nsec) requestors.

Abstract: A document processing system including a control structure having separated supervisory and document functions. The document functions, including a document buffer and document access control means are the sole means for accessing documents and the document function routines are selected from predetermined library of such routines. The system includes a flexible, expandable document structure incorporating information item blocks and indexing blocks related through pointers and means for applying visual and informational attributes to document text.

Abstract: A multiprocessor computer system having n parallel-operating computer modules which each include a processor module, a memory module and a data word reconstruction module, wherein each module of said system processes the same piece of data simultaneously and in parallel. The data words are applied to a reducing encoder so that code symbols stored in the relevant computer modules form a code word. The relevant error-correction code has a simultaneous correction capability in at least two code symbols. Each data word reconstruction module receives the entire code word in order to reconstruct the data word therefrom. Each computer module also has an input/output memory module. This module receives a coded data word which is decoded when it is presented again. Decoding is performed so that each bit in the input/output memory is mapped on at the most one bit of the associated memory module.

Abstract: In a multiunit data processing system, such as a multicontrol unit peripheral data storage system, a least busy one of the units requests work to be done from a busier unit. The busier unit, a work sending unit, supplies work to the work requesting or least busy unit. Work thresholds in the respective units determine when work is to be requested or transferred. In a data storage environment, the transferred work consists of data transfers to be achieved usually asynchronously to connected host activities, such as data transfers between a backing and a front store in a data storage hierarchy.

Abstract: An interface apparatus for interconnecting signal lines of a computer connector and a peripheral device connector with non-matching interconnect patterns having mismatched data lines or open inputs on handshake or control lines. A pair of conductive paths extend between the connectors, with each path interconnecting one data line of the computer connector with one data line of the peripheral connector. Lights indicate mismatched interconnection of the data lines, and a switch selectively reverses the interconnection of the data lines. Additional conductive paths extend between the connectors, each path interconnecting at least one handshake or control line of each connector with at least one handshake or control line of the other connector. Two pairs of interconnecting handshake lines are each provided with a switch in gang with the data line switch for selectively reversing their electrical interconnection.

Abstract: A fixed-point data/floating-point data converting apparatus has: a priority encoder with input terminals respectively receiving output signals from logic gates (first logic gates) for use in detecting whether or not all of the digits fixed-point data are "0", to obtain a number of continuous "zero" digits from the most significant digit of the fixed-point data, in accordance with the contents of the signals received thereby; a shifter for shifting the fixed-point data to the left by the number of digits of continuous "zero" digits, thereby obtaining a mantissa part; an adder for subtracting the number of continuous "zero" digits from a reference value, thereby obtaining an exponent part; and a data selector for generating the floating-point data in accordance with the subtraction results from the adder, the shift results from the shifter, all-zero data, and an output signal from the logic gate (first logic gate) for detecting whether or not all digits of the fixed-point data are "0", in response to the output

Abstract: In a microprogram-controlled processor, having an additional operating mode in which particular functions can be executed under direct hardware control, a mode latch signals whether microprogram instructions or directly controlled macro instructions are to be executed. The macroprogram instructions are conventionally executed. For the execution of directly controlled macro instructions, a control storage supplies a hardware control word associated with the macro instruction to be directly executed. The hardware control word contains a mode control bit for signalling that the direct hardware control mode is to be executed. The remainder of the hardware control word contains a plurality of direct control bits, each of which directly controls a hardware function. In an alternative embodiment multiple hardware control words are employed.

Abstract: A data base management system according to the invention stores, retrieves, and modifies data records within a digital computer data base, permitting access to related data records through partnerships joining record pairs. Partnership sets are employed to relate data records on a one-to-one, one-to-many, and a many-to-many basis. The invention facilitates the modelling of real world structures and events in a data base whose logical representation closely depicts those structures and events.

Abstract: A power supply control device is usable in a battery-driven electronic device, in which a power down mode is adopted when the battery is mounted.

Abstract: A system and method are disclosed for automatically refreshing a dynamic random access memory (DRAM) under a plurality of different operational conditions of an associated processor. When the processor is normally executing instructions it generates active signals which enable a generator circuit to generate timing signals. A hidden refresh circuit uses status signals and a first part of these timing signals to generate a refresh pulse during an opcode fetch cycle of each instruction being executed by the processor. A control circuit uses each refresh pulse and a second part of the timing signals to generate a row refresh signal to refresh a row in the DRAM indicated by a row address from a counter and a row address clock to increment the counter to the next row to be refreshed by the following row refresh signal.

Abstract: The present invention relates to a slow down circuit for use with a digital computer having a microprocessor ready line, an address bus and a data bus. The slow down circuit is comprised of an address decode logic unit for producing an inhibit signal when predetermined bit patterns appear on the address bus. The predetermined bit patterns represent special computer functions which require the computer to operate at normal speed. A slow down signal generator is connected to the address bus and the data bus for generating a bi-level signal. A combiner is connected to the address decode logic unit and the slow down signal generator for combining the inhibit signal and the bi-level signal to produce a control signal. The control signal has a first and a second logic level. When the control signal is at the first logic level the computer operates at normal speed.

Abstract: In a computer system, an instruction is executed. The results of the execution of the instruction are stored, and, simultaneously with the execution of the instruction, information is generated and stored which is related to the results of the execution of the instruction. This information is used by the computer system during the execution of subsequent instructions. The results of the execution of the instruction comprise a binary number. The information which is generated, simultaneously with the execution of the instruction, includes, inter-alia, a count of the number of binary "1" bits and binary "0" bits which constitute the binary number, and a set of addresses representing the address locations of each bit of the binary number which constitutes the stored results of the execution of the instruction.

Abstract: A solid state storage device is disclosed. The storage sections of the device are divided into two groups, with each group including at least one, and as many as four storage sections. A port is provided for delivering words to and receiving words from the sections. A data path between the port and the device is two words wide, with one word received from or delivered to each group. Each section includes a word storage register, with the registers of different sections in the same group being connected in a series fashion to provide a one word data path between the storage sections. Words stored or retrieved from a section are passed through its respective register. In a write operation, words to be stored are transmitted serially from register to register and captured by all sections simultaneously on the same clock cycle. Addressing means within each section then routes the word to the appropriate memory circuit within the section.

Abstract: A control program signal demodulating device comprises a control program demodulator for obtaining a demodulated output of a control program signal from a signal which is reproduced from a rotary recording medium which is recorded with at least the control program signal together with a video signal, where the control program signal indicates a control program including input and output commands and internal processing commands of an external device such as a computer which has a discriminating function and is coupled to a player which plays the rotary recording medium, a memory circuit for at least temporarily storing the demodulated output of the control program demodulator and producing the stored demodulated output, a selecting circuit for selectively producing data received from the memory circuit in response to a transmission request, an interface circuit for transmitting the data which is produced from the selecting circuit to the external device, and for receiving one or a plurality of control command

Abstract: A circuit for the rapid calculation of the real and imaginary parts of the h first harmonics of a signal supplied by a measuring device and particularly for the analysis of the voltage supplied by a non-destructive eddy current testing probe. The circuit comprises an analog-digital converter, a random access memory, and calculating means comprising a PROM, a counter, a multiplier, an accumulator and a sequencer.

Abstract: The communications system may include wireless two-way communications equipment having selectable functions and various operational features. Control modules each include mechanisms for providing indicia representative of the status of the features of the communications equipment and mechanisms for generating data for controlling the functions to be selected on the communications equipment. A group of the control modules are coupled to a panel module which selectively communicates with each of the control modules in the group. An interface circuit is coupled to a plurality of the panel modules for selectively communicating with each; the interface circuit includes a microprocessor for writing indicia data to each of the selected control modules via the selected panel module and reads the control data generated by the control modules. The periodic scanning and reading of information is utilized to ascertain changes in the data.

Abstract: A data stack for storing data at sequential locations in a memory and for transmitting the data in modes defined by commands from a host data processing system. A random access memory stores the data in sequential locations at addresses selected by a state signal generator comprising read only memory. The state generator generates the addresses and read/write control signals for the random access memory in response to the commands from the host system and a previous address provided by the generator.

Abstract: The invention provides a device and method for data processing.

Abstract: Data processing apparatus is described, comprising an array of data processing elements in rows and columns. Each element has a data register for input/output. Each column of data registers can be interconnected to form a serial shift path containing either (a) the even-numbered registers, (b) the odd-numbered registers or (c) all the registers. This allows data to be shifted out of the array, one row at a time, either from the even rows, the odd rows, or all the rows. Data can be shifted into the array in a similar way. The facility for selecting the even or odd rows is useful for handling interlaced image data.

Abstract: Arrangement for the input of address data to an integrated circuit (IC) via the same input/output (I/O) terminal pins utilized for the transfer of data is disclosed. The I/O data pins each have an output data latch and an address latch connected to the respective pin and positioned internally of the circuit's interface. A logic level is applied to each of those I/O data pins via a respective external resistor for normally biasing the pin to that logic level. A further I/O pin at the circuit's interface is connected to a common conductor positioned externally of the interface. Diodes are connected between selected ones of the I/O data pins and the common conductor in accordance with a desired address. A level controller responds to a power-on-reset (POR) gating signal to switch the common conductor between a high impedance state and a logic level which effects conduction by the diodes, to enter address data bits. Address latches in the IC store the entered address data bits.