Abstract: In an intelligent video terminal communicating with a central processor, a video memory controller is provided which performs a variety of data transfer operations in response to commands from a terminal processor. The data transfer operations include block reads and block writes, copying an entire screen data line or a portion thereof, scrolling an entire screen line or a portion thereof, filling a screen line or a portion thereof with a desired character, and independently scrolling a row segment within each of multiple independent screen display areas. In addition, the current location of the cursor within each screen display area can be monitored.Many of the data transfer operations are performed by the video memory controller in response to a single terminal processor command, thereby minimizing terminal processor interrupts.

Abstract: A digital signal processing apparatus is shown which is applicable for real time operation in the power spectrum of the detected outputs of ultrasonic Doppler blood flowmeter. The apparatus comprises a digital operating means, a memory means which is connected to said digital operating means to transfer data thereto and receive data therefrom, a fixed instruction generating portion for generating operating code for the digital operating means and addresses for the memory means, a read only memory for storing data of a squaring operation which has address inputs at the bit position selected as most suitable from the input data bus line of said digital operating means, an overflow detecting means when input data exceeds the region of the address input, and digital saturation circuit, whereby the power spectrum can be calculated by fundamental algorithm of WFTA having a smaller number of operating steps than algorithm FFT.

Abstract: Serial data transfer circuitry is provided for transferring data between a multiplicity of functional units of a VLSI semiconductor chip. Each functional unit is provided with a respective data register, the registers being adapted to receive information in parallel from and/or transfer information in parallel to their respective functional units. The registers are each serially connected in a closed loop for serially shifting data from one register to another. Data transfer from one functional unit to another is accomplished by transferring a data word in parallel to a source register from its respective functional unit, serially shifting data from the source register to a destination register and parallelly transferring the data word from the destination register to its respective functional unit. Control of the transfer is provided by a counter which counts the number of shifts required to transfer the data word from the source to the destination register.

Abstract: A personal computer attachment is provided for a display station of the type that communicates with a host computer (48). The display station has a display unit (10) and a keyboard (12) to which a personal computer system unit (14) is attached. The personal computer system unit typically supports floppy diskette drives (16) and a printer (18). The display unit includes a CRT (38), a regeneration buffer (42), a keyboard adapter (46) and a feature bus (44). The personal computer system unit includes a system bus, a microprocessor, memory, a keyboard adapter and I/O interface connected to the system bus. A display adapter (26 or 28) is connected to the I/O interface. An analog input switch (52) is disposed between the buffer (42) and the analog circuits driving the CRT (38). This switch has a second input from the display adapter (26 or 28) and is controlled from inputs from the keyboard (12) to selectively supply image data from the buffer (42 ) or the display adapter (26 or 28).

Abstract: A method of editing at a processor text formed by lines of characters received by the processor from a remote source whereby communication between the processor and the remote source is minimized. The method steps at the text processor include (a) generating a respective checking number corresponding to each line of characters received from the source; (b) modifying the received text to form a body of lines by selective addition, modification, or deletion of lines and characters; (c) generating a checking number for each line of modified text in the manner of step (a); and (d) associatively comparing the checking numbers of consecutive counterpart lines of the modified text with those of the received text and transmitting back to the remote source the entire text of only those lines which have been modified as denoted by said lines having checking numbers mismatching those of the received text.

Abstract: A universal interface adaptor circuit (UIAC) for connecting any one of a plurality of either of two general microprocessor types to a peripheral device using the same interface connections to selectively generate and supply either a WRITE ENABLE signal or a READ ENABLE signal to a peripheral device. A first of the two general types of microprocessors is used in multiplexed-bus multiprocessor (MBM) systems and the second of the two general types of microprocessors is used in non-multiplexed-bus microprocessor (NMBM) systems, where the microprocessors used in both the MBM and the NMBM systems each supply three output signals for determining whether the function is a READ or a WRITE function and the time of occurrence of such READ or WRITE function. The UIAC comprises logic array having three input terminals X, Y, and Z for receiving the three output signals from each of the microprocessors employed in either the MBM systems or the NMBM systems.

Abstract: An arithmetic system includes an arithmetic unit of a pipeline structure for executing arithmetic operations for instructions which require different arithmetic cycles. The arithmetic unit executes N arithmetics in pipeline for N instruction at maximum. Initiation of arithmetic operation for a new instruction in the arithmetic unit is indicated by an indicator which detects that each of the instruction executed in the arithmetic is N cycles before completion of the execution and allows arithmetic operation for the new instruction to be initiated in the succeeding cycle.

Abstract: A dual stream processor apparatus, for use in a multiprocessor computer system, is disclosed. The multiprocessor computer system includes at least a first processor and a second processor. A first apparatus and a second apparatus is included in both the first processor and the second processor for use when either the first or the second processor is inoperative. The first apparatus, disposed within the inoperative processor, suspends the functional operation of the inoperative processor. The second apparatus, disposed within the inoperative processor, transmits a miss signal to the other remaining functionally operational processor. When the other remaining processor receives the miss signal, it will not subsequently attempt to locate desired data in the cache of the inoperative processor. Rather, the other remaining processor will search for the desired data in the main memory in the event it cannot locate the data in its own cache.

Abstract: A self contained fixed rotating disk expansion board subsystem may be installed and connected at an expansion slot location of a host computer. The subsystem includes an enclosed head/disk assembly, and circuit elements mounted on a printed circuit board which includes a connector for connecting to the control, data and address buses of the host computer at the expansion slot location. The head/disk assembly is mounted to a mounting substrate which may be the circuit board or which may be a frame to which the circuit board is also attached. Input/output routines are preferably provided to enable the host computer to make use of the subsystem without software driver modifications in the host operating system.

Abstract: A computer system has a CPU, a main memory and an additional memory storage which is difficult from the main memory and an external storage. The additional storage may transmit data with the main memory and/or the CPU.

Abstract: A data processing system having a central processing unit (CPU) capable of performing binary and decimal arithmetic software instructions is disclosed. The CPU includes a microprocessor which executes the binary arithmetic software instructions under firmware control. Also disclosed is apparatus utilizing a programmable memory and logic circuits that are used to subtract two operands and to generate and temporarily store a digit equal nine indication when the result of subtracting the two operands has a value of nine.

Abstract: A microprocessor system includes a CPU device with on-chip or off-chip memory, and data and control busses for accessing memory and/or peripherals. The peripheral circuitry includes one or more channels for input and/or output of data, wherein various characteristics of the treatment of data in the channel are controlled by the program being executed in the CPU. In one embodiment analog input and output channels are included, and the A-to-D or D-to-A conversion rates are selected by executing a data output instruction by the CPU. The cut-off points of the filters are likewise selected. The A-to-D converter loads a first-in first-out memory which is read by the CPU in burst mode when filled. Likewise, the CPU loads digital data to a first-in first-out memory in the output channel, and then the D-to-A converts at its selected rate.

Abstract: A data processing system for vector processing having a main memory accessible in parallel by a plurality of processors, each processor having a cache memory, wherein, in response to a storage instruction given to the main memory by a processor, a main memory block of a given size (BS) and having a give start address (B) and containing element data spaced at an interelement distance (D) being preempted as a result of the storage instruction, a single block address invalidation takes place at each cache memory previously having data stored at that main memory location, the single block address invalidation corresponding to (BS/D) cache address invalidations, whereby repeated sequential individual cache address invalidation operations for each address in the preeempted block no longer are required.

Abstract: An improved multiplier is disclosed for multiplying a first operand times a second operand, which includes a Booth-type translator having an input connected to receive the first operand, for translating the binary expression of the first operand into a sequence of signed digits. The multiplier further includes a partial product generator having a first input connected to the output of the translator and a second input connected to receive the second operand, for multiplying the translated first operand times the second operand and outputting partial products consisting of signed digits. The multiplier further includes an array of adders, each adder having an input connected to two of the signed digits output from the partial product generator, for providing a sum consisting of a sequence of signed digits.

Abstract: A vernier address scale reduces the number of addressable memory locations required for numerical look-up tables. Read-only memories (ROMs) store the data of linear or non-linear functions. Decoders determine which ROM is selected and advantage is taken of accuracy improvement as numbers become large by dropping least significant bits as the vernier address scale moves from one ROM table to another. Accuracy is further improved by using a method of one-half level quantization step for rounding. This reduces the size of numerical tables for math processing of reciprocals, roots of numbers, powers of numbers, logarithms, trigonometric and exponential functions.

Abstract: A circuit comprising first, second and third latches selectively extends a cycle of a clock signal of a memory system in response to a control signal. A second clock signal having a frequency which is a predetermined multiple of the clock signal of the memory system is coupled to an input of the second and third latches. The first latch receives first and second control signals indicating the detection of parity errors in the memory system and suspends or delays the normal transition of the third latch which provides the memory system clock signal, thereby extending a cycle of the clock signal. The second latch resets the first latch which thereafter resets the third latch causing the clock signal to return to normal cycle operation.

Abstract: A logic state analyzer allows a user to include symbols defined in source program listings, as well as other specially defined symbols, in the trace specification. Such symbols represent unique individual values or ranges of values. The resulting trace list includes these symbols, and where possible, all address, operands, etc., are expressed in such terms. When those symbols are relocatable entities produced by compilers and assemblers the result is that the user is freed from having to duplicate the relocation process to specify absolute values in the trace specification, and later reverse it to interpret absolute values in the listing in terms of symbols originally defined in the source programming. A further result is that the states within an arbitrary finite state machine can be assigned descriptive labels, with the trace specification and trace listing subsequently expressed in those terms. Trace values can also be represented relative to a symbol.

Abstract: A programmable status register arrangement which enables the status of a plurality of status registers in a system to be checked simultaneously including fusible links connected to the outputs of the status registers whereby a user of the arrangement can program it to control the transmission of status signals by the plurality of status registers.

Abstract: A portable calculator and recordal device is disclosed herein which includes a pad of paper and an electronic calculator which is movably disposed over the pad on a sliding carriage in association with a printer whereby information entered into the calculator may be printed onto the paper. The sliding carriage is adapted for manual removal from the pad of paper for easy reference. Apparatus is provided for printing at variable heights as paper is expended. The device is especially useful for printing a variety of transactions on the paper and associated recordal sheets.

Abstract: A binary coded decimal number division apparatus in which a quotient represented in a binary coded decimal notation is determined on digit-by-digit basis by using a quotient prediction table and a group of multiple value registers and in which a predicted quotient read out from the quotient prediction table is used intact when the predicted quotient is correct while otherwise the predicted quotient is decremented by one, wherein the values stored in the quotient prediction table together with redundant bit are previously modified to (0110).sub.2 to (1111).sub.2 in the binary coded decimal representation. The multiple value register is selected by using three of the four bits of the modified predicted quotient, while upon determination of the quotient, the value used for modification is subtracted from the output value of the quotient prediction table to thereby derive the predicted quotient of one digit.