Abstract: A method and associated apparatus is provided for using data stored in one non-volatile memory to locate the next memory address in which to write data in another non-volatile memory of an electronic postage meter, comprising the steps of and associated apparatus for providing a first non-volatile memory for storing data therein including cumulative piece count data corresponding to the number of completed postage transactions, providing a second non-volatile memory for storing accounting data sequentially therein for each one of a predetermined number of trip cycles of the postage meter which number corresponds to the number of individually addressable trip cycle memory locations in the second non-volatile memory and defines a modulus of the second non-volatile memory, retrieving the cumulative piece count data from the first non-volatile memory during a power up cycle, dividing the cumulative piece count data by the modulus of the second non-volatile memory, and using the remainder resulting from the divisi

Abstract: A circuit arrangement for supplying interrupt requests signals from a peripheral unit to a central processing unit of a computer system over a common control line, without a priority scheme. A blocking circuit is provided such that the first interrupt signal on the common control line blocks any further interrupt signals on that line until the interrupt has been processed. Since no further interrupts are possible, the interrupt acknowledged signal from the central processing unit need not contain the address of the external unit having requested the interrupt nor need there be provided a circuit to process the interrupt acknowledge signal in the peripheral unit. An interrupt signal present on the common interrupt line blocks generation of subsequent interrupt signals from reaching the common interrupt line by a combination of the two interrupting switches together with a delay after the first switch.

Abstract: A personal computer having an interactive all points addressable display terminal (44) and a cursor positioning device (52) is provided with a keyboard (28) for inputting alphanumeric character strings not exceeding a predetermined maximum length. Once the desired alphanumeric character string has been input, it can be selected as the current cursor character. As the selected current cursor character, the alphanumeric character string is displayed on the all points addressable display and movable by said cursor positioning device. When the alphanumeric character string is positioned at a desired location on the all points addressable display, it can be fixed in that location by reading the alphanumeric character string data into the display buffer.

Abstract: A memory refresh circuit controls the refreshing of dynamic RAM included in a system wherein a control store outputs micro-code instructions to control the system operation in response to sequences specified by a sequence and interrupt logic circuit (SIL). A counter transmits certain counts of system machine cycles to an array logic device. In response to one count, the array logic device generates a memory refresh request signal which is applied to a RAM address logic circuit (RAL). The RAL monitors the micro-code instruction output at each machine cycle to determine whether the instruction will access the dynamic RAM during that machine cycle, and if no memory access is detected, the RAL generates a signal to initiate a memory refresh operation, which operation requires two machine cycles to complete.The array logic device also monitors the micro-code instructions to determine if and when a refresh operation was initiated.

Abstract: A rate calculator for calculating, displaying and continuously updating the rate of occurrence of events. Manually entered signals indicative of the occurrence of an observed event trigger a resettable counter for counting the number of events. A clock is activated by the first entry signal for measuring the time duration from the first entry and a processor responds to the counter and the clock for cumulatively calculating the rate of occurrence of each event from the second event on. A display of the calculated rate is provided for visual perception.

Abstract: This invention relates to a register and more specifically to register control in a data processing system. In general, a number of control registers are theoretically required that is less than the maximum number which can be designated, and only the required number of registers are mounted as hardware. In order to add functions or to provide compatibility with other systems, it is sometimes required to use a register that is not mounted as hardware, or to use the registers mounted as hardware for conflicting purposes. Virtual registers are accordingly provided for at address locations in the memory of the processing system. However, if only the registers to be added are thusly provided for in the memory, the instructions must be executed by distinguishing between register access and memory access, in accordance with register number, etc. Thus, this invention provides a number of virtual registers for instance equal to the number that can be designated.

Abstract: Apparatus for monitoring and displaying the activity of an information processing system, such as a central dictation system, having plural recorders, plural originating stations for supplying information jobs to be recorded on the recorders, and recovery stations for recovering information jobs from those recorders. The activity which is monitored and displayed includes the availability of respective recorders to receive information from originating stations, the lengths of information jobs which have been recorded and now await recovery, the expected recovery delay in recovering a new information job to be recorded on a recorder, and the number of information jobs in each recorder that are awaiting recovery. The apparatus includes a processor which senses the aforementioned activity and controls a video display for displaying same.

Abstract: An ALU, performing selected operations on input operands in a predetermined clock cycle, uses means for detecting a carry propagation path greater than a predetermined number of consecutive bit positions to cause a stretching of the clock cycle. Since such a long carry propagation path is detected for only a very small percentage of all operations, the cycle is normally shorter than otherwise possible, AND, thus, the performance of a system using such an improved ALU is increased.

Abstract: This device permits the distribution of the access to a RAM memory RAM (14) among a plurality of users (U1, U2, U3), the access being effected in an asynchronous manner. Certain users (U2, for example) can access the memory at adjoining addresses by means of a single row precharge cycle, the column access cycles (CAS) being successively effected during a single row (RAS) access cycle. One can thus considerably reduce the access time of the memory (14) when a large quantity of data must be read into the memory or written into it.Application to teletext terminals where the users of the memory can be the CPU, the video processor, and a teletext data receiver.

Abstract: A test module is provided for troubleshooting and diagnosing hardware failures in the interface logic to an asynchronous microprocessor bus at true operating speed until a fault occurs. If a fault is detected, the circuit will halt a microprocessor under test coupled to the asynchronous microprocessor bus and freeze the state of the bus signal lines. The microprocessor under test has bit pattern sets therein. A test microprocessor has test pattern sets stored in internal memory. Test pattern latches are coupled to the test microprocessor for sequentially latching the test pattern sets. Address bus latches and data bus latchs are coupled to the asynchronous bus for latching the state of the address lines as a pattern under test.

Abstract: The object of the present invention is to provide an improved convolution processor that requires no multiplication operations and can easily be implemented digitally.

Abstract: Circuitry for generating scalar products and sums of floating point numbers with maximum accuracy and circuitry and a method for electronic computers by which scalar products of floating point numbers of the type pi, qi, ES(b,l,e1,e2) are summed with full precision in a fixed point representation by means of a summing unit (ALU) and one or more accumulator registers (ARC1, ARC2) with cells (Ai, j) for storing of codes of a base b having a length (2l+ 2 e1+ 2e2) for fixed point representation and certain overflow positions. By control means (SHR, E, Contr) the mantissas of products are delivered depending on the value of the respective exponents into the summing unit (ALU). By control means (RD, Contro), rounding operations ( .circle. , , .gradient., .increment.) demanded by the higher level computer are performed, and a rounded floating point number (.quadrature. c .epsilon. S(b,l,e1,e2)) and overflow (OF) and underflow (UF) criteria are delivered.

Abstract: A single instruction, multiple data stream parallel computer using bit-serial arithmetic whereby the machine's basic operation is performing Boolean operations on huge vectors of 0's and 1's. The machine utilizes an architectural approach whereby the memory of a conventional machine having 2.sup.k words each t bits long, is reorganized into p registers each 2.sup.k bits in length and adding processor logic to each bit position of the registers and a communication network being added which allows for the 2.sup.k pieces of processing logic to interact. This machine is capable of executing a wide variety of algorithms at a speed of 2.sup.k /p to 2.sup.k /p.sup.2 faster than conventional machines. The machine provides for an ability to handle a variety of algorithms by interconnecting the individual processor elements in a general interconnection network capable of performing a permutation of n bits held one in every processor element in a time of (O(log(n)).

Abstract: A unit transformation circuit transforms three discrete input signals into a set of transform coefficient signals characteristic of a "collapsed" Walsh-Hadamard transform. The unit transformation circuit includes two tiers of arithmetic networks. In the first tier, a pair of arithmetic networks generates (A) first sum and difference signals from the first and second input signals and (B) second sum and difference signals from the second and third input signals. Arithmetic networks in the second tier generate a set of coefficient signals from (A) the sum of the first and second sum signals (B) the sum of the first and second difference signals and (C) the difference between the first and second difference signals. The unit transformation circuit forms a fundamental circuit element from which more complex circuits are constructed capable of transforming larger numbers of discrete input signals.

Abstract: A digital computer memory prefetches, or reads ahead, a next sequential, odd, address data word from a backing memory store containing all such odd address data words to a high speed buffer register simultaneously that the memory fetches the immediately preceding, even address data word from a backing memory store containing all such even address data words to that requestor-user, one of selective one(s) of a multiplicity of such requestor-users with which the memory communicates, which is addressably reading such even address data word. Selective one(s) of the requestor-users, which one(s) is (are) predominantly sequential in successive read addressings, does (do) enable such prefetching through a unique signal communicated to the memory. Remaining requestor-users do disable, via the alternative condition of the same signal, any prefetching; causing thereby no disturbance to the priorly read-ahead, odd address, data word.

Abstract: A method and apparatus for transferring data in parallel from a smaller to a larger register is described, in which the larger register comprises a first and a second set of master and slave latches with a one shot employed for clocking the master latches in the first set. In operation, a first word from the smaller register is latched into the first set of master latches in response to an output from the one shot which occurs on the trailing edge of a clock pulse applied to the larger register. On the leading edge of a subsequent clock pulse applied to the larger register, a second data word is latched in the second set of master latches. Immediately thereafter the first and the second set of slave latches are opened for transferring the first and second words at their inputs to their outputs in parallel. Following the transfer of the first and second words to the outputs of the first and second set of slave latches, the slave latches close, latching the first and second words.

Abstract: A circuit and technique of operation thereof are disclosed for a multimaster CPU system wherein a memory may be accessed during program operation in an average time less than that of the memory access time specification. This technique has particular usefulness in programs contained in relatively slow read-only-memory wherein a significant portion of the addresses related to memory are sequential. In optimum utilization, each master CPU has a dedicated PROM card which can only be enabled by the specified CPU. This configuration prevents additional master CPU's from interfering with the time saving benefits of early memory addressing.

Abstract: In a storage hierarchy system, a part of data stored in a main storage in held as a copy by a buffer storage of a smaller capacity and higher speed than the main storage. A processor fetches data from the buffer storage or stores data in the buffer storage at a high speed. A buffer storage control system includes a first buffer directory and a second buffer directory. The first buffer directory and the buffer storage are accessed by an address for a fetch request, while the second buffer directory and the buffer storage are accessed by an address for store request, whereby competition for the access to the buffer storage between the fetch and store operations is reduced.

Abstract: An embodiment of the invention includes a binary linear phase response filter having a plurality of weighted outputs and a summing circuit which sums groups of the weighted outputs. A polarity inverting mechanism is provided for selectively changing the polarity of the summed outputs from the summing circuit means. An encoding circuit controls the polarity selection in accordance with the logic rule for converting non-return to zero (NRZ) data into return to zero data. Another summing circuit sums the outputs of the polarity inverting mechanism and provides a filtered multilevel data output.

Abstract: An output compare system and method for automatically controlling multiple outputs in a data processor includes an output compare mask register for holding a set bit therein. An output compare data register is coupled to a control output of the output compare mask register for holding a data bit therein. Apparatus for initiating an output compare function are coupled to a control input to the output compare mask register whereby the data bit will be transferred to an output of the data processor if the set bit is present. The system and method allow for simultaneous utilization of multiple output compare functions to achieve one-cycle-wide pulses on a timer output pin.