Abstract: In a cache tag integrated on an SRAM with a memory cache, laser fuses are programmed to indicate which, if any, tag subarrays in the cache tag are not functioning properly. In addition, the burst length of the SRAM is increased to reduce the number of tag subarrays necessary for operation of the cache tag so any nonfunctional tag subarrays are no longer necessary. In accordance with the indications from the programmed laser fuses and the increased burst length, logic circuitry disables any nonfunctional tag subarrays, leaving only functional tag subarrays to provide tag functionality for the memory cache. As a result, an SRAM that is typically scrapped as a result of nonfunctional tag subarrays can, instead, be recovered for sale and subsequent use.

Abstract: A method is adopted in a control apparatus for controlling ID information stored in a storage medium in conjunction with a terminal for reading the ID information from the storage medium and used to catalog information for the storage medium into a memory employed in the control apparatus. In an operation to catalog information into the memory of the control apparatus, the terminal receives the information, reads the ID information from the storage medium and transmits the information and the ID information to the control apparatus and the control apparatus catalogs the information and the ID information in the memory by associating the information with the ID information.

Abstract: A data storage device includes one or more non-volatile, blockwise erasable data storage media and a mechanism for sanitizing the media in response to a single external stimulus or in response to a predetermined physical or logical condition. Optionally, only part of the media is sanitized, at a granularity finer than the blocks of the medium. Setting a flag in an auxiliary nonvolatile memory enables an interrupted sanitize to be detected and restarted. Optionally, a “death certificate” verifying the sanitizing is issued. Preferably, the media are configured in a manner that allows atomic operations of the sanitizing to be effected in parallel.

Abstract: A storage system according to an embodiment of the present invention has a storage and a controller. The storage has an interface for connecting it to a storage of another storage system via a communication line, and a remote copy module transferring predetermined data to the another storage system, not via the controller, based on a data transfer command from the controller. The controller has a remote copy control module transmitting to the remote copy module, at reception of a notification of account attribute movement from an account monitor module monitoring the account attribute movement, a data transfer command for transferring predetermined data to the other storage system, not via the controller.

Abstract: The present invention allows a user to customize the configuration sequence of a configurable system on a chip (CSoC), thereby adding considerable flexibility to the configuration process. The present invention also provides certain features, transparent to the user, which optimize system resources and ensure the correct initialization of the CSoC. The CSoC leverages an on-chip central processing unit (CPU) to control the configuration process of the configurable system logic (CSL). Advantageously, the CSL configuration memory cells as well as other programmable locations in the CSoC are addressable as part of a system bus address space. The system bus is a multi-use structure that can be used for both configuring and reading of memory cells. In this manner, the CSoC optimizes system resources.

Abstract: One or more mapping data structures are maintained containing mappings of logical flash memory addresses to physical flash memory addresses. Each mapping data structure has a predetermined capacity of mappings. A master data structure is also maintained containing a pointer to each of the one or more mapping data structures. Additional mapping data structures are allocated as needed to provide capacity for additional mappings. Each time a mapping data structure is allocated or de-allocated the pointers in the master data structure are changed accordingly.

Abstract: One or more secondary data structures are maintained containing mappings of logical flash memory addresses to physical flash memory addresses. Each secondary data structure has a predetermined capacity of mappings. A master data structure is also maintained containing a pointer to each of the one or more secondary data structures. Additional secondary data structures are allocated as needed to provide capacity for additional mappings. One or more counters associated with each of the one or more secondary data structures, respectively, provides an indication of when each of the one or more secondary data structures reaches the predetermined capacity of mappings.

Abstract: Methods for updating an electronic device having a non-volatile memory are disclosed. An embodiment of the present invention may permit the update of an electronic device from a first code version to a second code version using a fault-tolerant, bank-by-bank method. An update package comprising update instructions may be received via a public and/or wireless network, and the update instructions may be used to convert the first code version to the second code version. The bank order of the conversion may be specified in the update package, and may be non-sequential.

Abstract: Managing memory allocations and de-allocations with a stack, and managing hardware initializations and de-initializations with another stack. A stack may store de-allocate information. Another stack may store de-initialization information. The techniques may be applied to allocating/de-allocating memory for parts of a device driver, initializing/de-initializing parts of hardware, and initializing/de-initializing parts of software.

Abstract: A flash driver tracks data stored in a flash memory device through the use of logical-to-physical sector mapping. The mapping is stored in a data structure and allows data to be written into the next free physical sector in the flash memory medium. Write operations complete quickly, because there is no need to perform an erase operation in order to write new data on to the flash memory medium. Data loss due to power interruption during a write operation is also minimized by the described implementations. The logical-to-physical sector mapping stored in data structure is backed-up on the flash memory medium. In the event there is a catastrophic power interruption, logical-to-physical sector mapping can easily be reestablished by scanning the backed-up mapping in the flash memory medium. The backed-up information can be stored in a spare portion of a NAND or NOR flash memory medium.

Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication connections are used for bi-directional data communication with an external device(s), such as a processor or other memory controller. In one embodiment a non-volatile synchronous memory device includes an array of memory cells arranged in a plurality of addressable banks. A bank buffer circuit is coupled to each of the banks. Each of the buffers can store data from a row of memory cells contained in a corresponding bank. A method of operating a synchronous flash memory includes storing instruction code in each array block and copying the instruction code from a first array block to a buffer circuit, during a write operation, so that the instruction code can be read from the buffer circuit during the write operation.

Abstract: The invention provides a cache management system comprising in various embodiments pre-load and pre-own functionality to enhance cache efficiency in shared memory distributed cache multiprocessor computer systems. Some embodiments of the invention comprise an invalidation history table to record the line addresses of cache lines invalidated through dirty or clean invalidation, and which is used such that invalidated cache lines recorded in an invalidation history table are reloaded into cache by monitoring the bus for cache line addresses of cache lines recorded in the invalidation history table. In some further embodiments, a write-back bit associated with each L2 cache entry records when either a hit to the same line in another processor is detected or when the same line is invalidated in another processor's cache, and the system broadcasts write-backs from the selected local cache only when the line being written back has a write-back bit that has been set.

Abstract: A method and system for optimizing use of signal paths on a DRAM interface. Signal paths that have a ‘don't care’ status during DRAM refresh are assigned to communication with another device. Onset of the refresh procedure triggers diversion of shared signal paths away from the DRAM to the other device for the duration of the refresh the shared signal paths include at least some of the address and data signal paths.

Abstract: A computer system comprises a memory controller and a synchronous non-volatile memory device coupled to the memory controller via a main memory bus. The synchronous non-volatile memory device has external interconnects arranged in a manner that corresponds to interconnects of a synchronous dynamic random access memory device. The synchronous flash memory device, however, comprises a reset connection, and a Vccp power supply connection correspond to first and second no-connect (NC) interconnect pins of the synchronous dynamic random access memory. In one embodiment, the synchronous non-volatile memory device has a command interface comprising a write enable connection (WE#) to receive a write enable signal, a column address strobe connection (CAS#) to receive a column address strobe signal, a row address strobe connection (RAS#) to receive a row address strobe signal, and a chip select connection (CS#) to receive a chip select signal.

Abstract: The present invention provides for a plurality of partitioned ways of an associative cache. A pseudo-least recently used binary tree is provided, as is a way partition binary tree, and signals are derived from the way partition binary tree as a function of a mapped partition. Signals from the way partition binary tree and the pseudo-least recently used binary tree are combined. A cache line replacement signal is employable to select one way of a partition as a function of the pseudo-least recently used binary tree and the signals derived from the way partition binary tree.

Abstract: The invention is used in a virtual machine monitor for a multiprocessing system that includes a virtual memory system. During a software-based processing of a guest instruction, including translating or interpreting a guest instruction, mappings between virtual addresses and physical addresses are retained in memory until processing of the guest instruction is completed. The retained mappings may be cleared after each guest instruction has been processed, or after multiple guest instructions have been processed. Information may also be stored to indicate that an attempt to map a virtual address to a physical address was not successful. The invention may be extended beyond virtual machine monitors to other systems involving the software-based processing of instructions, and beyond multiprocessing systems to other systems involving concurrent access to virtual memory management data.

Abstract: Systems and methods for providing on-demand memory management. In response to a mapping request from a device driver or other program, a first portion of the memory is mapped to one or more virtual addresses in a first region of a virtual memory space so that it can be directly accessed by the CPU. In response to an unmapping request the first portion of the memory is unmapped. Mapping and unmapping requests may be made at any time.

Abstract: This invention is a system and method for configuring or modeling a data storage environment in accordance with workload and performance characteristics and by using selected correlation characteristics of logical devices storing data on a data storage system in the environment.

Abstract: The preferred embodiments described herein provide a method for reading data in a write-once memory device using a write-many file system. In one preferred embodiment, data traffic between a data storage device and a write-once memory device is redirected so that file system structures of a write-many file system do not overwrite previously-stored file system structures. Data traffic between the write-once storage device and a data reading device is also redirected so that a current file system structure of the write-many file system is provided to the data reading device instead of an out-of- date file system structure. In another preferred embodiment, a non-volatile write-many memory array is provided in the write-once memory device to store file system structures of a write-many file system.

Abstract: Power conservation may be achieved in a front end system by disabling a segment builder unless program flow indicates a sufficient likelihood of segment reuse. Power normally spent in collecting decoded instructions, detecting segment beginning and end conditions and storing instruction segments is conserved by disabling those circuits that perform these functions. An access filter may maintain a running count of the number of times instructions are read from an instruction cache and may enable the segment construction and storage circuits if the running count meets or exceeds a predetermined threshold.