Abstract: An arithmetic unit includes a switching device 16 and a cache controller 19. The switching device 16 determines whether desired data to be read by the CPU 11 is in a RAM 14, and allows, depending on a result of the determination, the CPU 11 to directly read the desired data from a ROM 13. The cache controller 19 controls a cache 12 so that the RAM 14 is initialized based on cache data corresponding to the desired data stored in the cache 12. In an arithmetic unit having a CPU, a cache, RAM, and ROM configured in the above manner, the time required for a startup process is reduced.

Abstract: A method and system for mirroring and archiving mass storage. A primary mass storage and a secondary mass storage are synchronized to contain the same data. Thereafter, a primary system tracks changes made to the primary mass storage. These changes are consolidated periodically into update files, the consolidations representing changes made to the primary mass storage during a time interval that ends when the primary mass storage is in a logically consistent state. These update files contain only those changes necessary to represent the modified state of the primary mass storage at the time of the update. The primary system then transfers the update files to a secondary system to bring the secondary mass storage current with the primary mass storage. The consolidation minimizes the amount of information that must be transferred and therefore allows for a relatively low band width communication channel.

Abstract: An arrangement is provided for improving the performance of a computing system, specifically for improving the efficiency of code cache management for a system running platform-independent programs with a small memory footprint. The code cache of such a system is continuously monitored during runtime. When a condition warrants performing code cache management, the priority-based code cache management is performed based on selective code garbage collection. The code garbage collection is conducted selectively for dead methods in the code cache based on probabilities of the dead methods being reused.

Abstract: An access control unit and method is proposed for use with an SDRAM (Synchronous Dynamic Random-Access Memory) device to control each round of burst-transfer type of access operation on the SDRAM device. The proposed access control unit and method is characterized by that the column-address strobe signal involved in each round of the burst-transfer access operation is continuously set at active state for a period of clock pulses equal in number to the specified burst length of the burst-transfer access operation, rather than just for a period of one pulse. This feature allows external circuitry to arbitrarily change the burst length, and also allows no use of burst-stop command or a precharge-interrupt method to stop each round of the burst-transfer access operation, allowing the access control logic circuit architecture to be more simplified than the prior art.

Abstract: The present invention permits backup processing suited to data characteristics relating to backup target data by means of a method that is simple for the user. Data characteristic classification definition information, in which data characteristic IDs correspond with one or more data characteristic types respectively, and mapping information, in which backup destination server information corresponds with one or more data characteristic IDs respectively, are prepared. The backup source server 3 sets data characteristic IDs in each of the backup target files on the basis of metadata of designated backup target files and of the data characteristic classification definition information, and then determines backup destination servers 6A to 6C for each of the backup target files on the basis of the set data characteristic IDs and mapping information and transmits the backup target files to the determined servers 6A to 6C.

Abstract: A method and system for using XML for both a protocol layer and application data are described. The method comprises the steps of initiating a connection by a client to a server to form a session, responding by said server to said client indicating that said connection has been successfully completed, submitting a request by said client to said server for service, responding by said server to said client by providing said service and terminating the connection by said client. A session is maintained and a plurality of requests for service by a client and a server responds to those requests by providing the requested service or an error message. The session is maintained until all requests made by a client have been serviced and the requests made by a client may be either synchronous or asynchronous. The system comprises a client and a server coupled to said client by a communications link.

Abstract: A method and mechanism for generating a snapshot in a computing system. On initiating a snapshot of a first storage, the content of a portion of the first storage that includes at least one block is copying to snapshot storage and a copied indication for each copied block is recording in a copy map. Responsive to any write request to a block for which no copied indication has been recorded in the copy map, the content of the block is copied to the snapshot storage, prior to writing to that block. The content of other blocks for which no copied indication has been recorded in the copy map is successively copied to the snapshot storage. A copied indication for each copied block is recorded in the copy map. The successive copying can be performed as a background task.

Abstract: A system, method and apparatus is disclosed for providing real-time access to a network organized repository of data. The system includes a computing system including one or more computers having one or more processors for executing a first set of program instructions and a first memory for storing the first set of program instructions; and a server, in communication with the computing system, the server having one or more processors for executing a second set of program instructions and a second memory for storing the second set of program instructions, the server being configured to support one or more users and to provide shared access to one or more telecommunication computer software programs, the server being coupled to one or more resources for managing, communicating and the storing data and the computer software programs.

Abstract: Methods and systems for operating automotive computing devices are described. In one embodiment, a small amount of static RAM (SRAM) is incorporated into an automotive computing device. The SRAM is battery-backed to provide a non-volatile memory space in which critical data can be maintained in the event of a power loss. Circuitry is provided to ensure that the SRAM receives back up power from the battery at the appropriate time. Software manages the SRAM and the other storage assembly components and makes use of virtual paging or virtual addressing techniques to keep track of where various pages, including object store pages, are stored in the system. The software knows exactly where all of the object store pages are stored so that in the event of a power loss, the page locations are known and hence the pages can be used when power is restored.

Abstract: A method of safeguarding program parts which are critical to safety against inadvertent execution is described. In this method, at least one program part is executed in a predetermined chronological sequence. At a certain time in the execution, a pattern is generated. At least at one later time, a check is then performed to determine whether the pattern is present. If the pattern is not present, the execution of the respective program part is terminated. A memory device for executing such a method is also described.

Abstract: Methods and apparatus for programmable logic devices including embedded processors having a dual-port SRAMs. A programmable logic integrated circuit includes a programmable logic portion having a plurality of logic elements, programmably configurable to implement user-defined combinatorial or registered logic functions, and an embedded processor portion coupled to the programmable logic portion. The embedded processor portion includes a processor, and a memory block coupled to the processor. The memory block includes a first plurality of memory cells for storing data, a second plurality of memory cells for storing data, a first port coupled to the first and second pluralities of memory cells, a second port coupled to the first and second pluralities of memory cells, and an arbiter coupled to the first port and the second port.

Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication connections are used for bi-directional data communication with an external device(s), such as a processor or other memory controller. The memory can output data from storage registers on the data communication connections during a series of clock cycles to provide a burst of register data. The memory can also provide the register data in accordance to a defined clock latency value. The register data can include status data, operating setting data, manufacture identification, and memory device identification.

Abstract: A recording medium holder enables a user to easily find a desired recording medium from recording mediums that the user manages. The recording medium holder includes a recording medium holding unit for holding a plurality of recording mediums, a liquid crystal displaying unit for displaying each of the plurality of recording mediums held in the recording medium holding unit by an icon, and an information displaying unit for displaying information of a recording medium that corresponds to an icon clicked in the liquid crystal displaying unit, the information including ID information, title information, index information, and other information. The information is read out from the recording medium at a first click, and from a storing unit at a second click and after.

Abstract: This invention concerns an optimised management method for allocating memory space of an onboard system to a data structure and a corresponding onboard system. The object code packets and the data packets being discriminated, and the memory being subdivided into addressable elementary memory blocks, the method consists in allocating (A1) to the object code packets a set of elementary memory blocks located in a first memory space (MS1) to addresses substantially adjacent and to the data packets another set of elementary memory blocks located in a second memory range (MS2). This enables to avoid fragmentation of the memory zone, during successive installations/deinstallations and to implement very easily an optimal defragmentation procedure, adapted to each type of data, code or application data.

Abstract: To provide a DRAM that reduces access latency during refresh and performs refresh for any non-accessed bank in parallel with normal memory accesses. Furthermore, the DRAM allows access to a bank that is undergoing refresh. The DRAM includes a circuit for directing refresh execution by comparing bank address of both access and refresh operations, a circuit for specifying a bank address of the memory cells to be refreshed, a circuit for addressing a row address of the memory cells to be refreshed in the specified bank, a means for refreshing the memory cells, and a means for accessing the memory cells directly after refresh without denying the access request.

Abstract: One or more secondary data structures are maintained containing mappings of logical flash memory addresses to physical flash memory addresses. Each secondary data structure has a predetermined capacity of mappings. A master data structure is also maintained containing a pointer to each of the one or more secondary data structures. Additional secondary data structures are allocated as needed to provide capacity for additional mappings. One or more counters associated with each of the one or more secondary data structures, respectively, provides an indication of when each of the one or more secondary data structures reaches the predetermined capacity of mappings.

Abstract: In an example embodiment, an adaptive method of prefetching data blocks from an input/output device comprises predicting the address of each read operation reading a data block from the input/output device, the prediction based on the address of the immediately preceding read operation from the input/output device; tracking, for each read operation, whether each read operation reads a block data from the same address of the input/output device predicted for the read operation; and prefetching a data block for a read operation from the input/output device in accordance with the state of a state machine, the state of the state machine depending upon whether immediately preceding read operations read a data block from the same address of the input/output device predicted for the read operations.

Abstract: An improved method and system for client-side caching that transparently caches suitable network files for offline use. A cache mechanism in a network redirector transparently intercepts requests to access server files, and if the requested file is locally cached, satisfies the request from the cache when possible. Otherwise the cache mechanism creates a local cache file and satisfies the request from the server, and also fills in a sparse cached file as reads for data in ranges that are missing in the cached file are requested and received from the server. A background process also fills in local files that are sparse, using the existing handle of already open server files, or opening, reading from and closing other server files. Security is also provided by maintaining security information received from the server for files that are in the cache, and using that security information to determine access to the file when offline.

Abstract: A semiconductor memory device is provided for preventing a late-write from disturbing a refresh operation and also for reducing a current consumption in a write cycle with execution of the late-write. Upon a transition of an address ADD, an address transition detector circuit detects this address transition. Upon receipt of a result of detection by the address transition detector circuit, a state control circuit judges an operation to be executed, from an output enable signal /OE and a write enable signal /WE, and then outputs any of a read statement RS, a write statement WS, and a refresh statement FS. According to a clock signal ACLK, input signals such as addresses are taken for executions of operations based on the statements.

Abstract: In one embodiment of the present invention, a process that uses a first processor is provided. The process includes the operation of blocking by the first processor of completion by a second processor of a configuration cycle. The process also includes the operation of selecting by the first processor of one procedure from a plurality of procedures that are associated with respective types of circuitry that may be used to permit the first processor to control a device. The one procedure is associated with one of the respective types of circuitry that is actually available to be used by the first processor.