Abstract: A system and method for mail server backup. In one embodiment, the method may comprise storing one or more messages on a mail server, where each message is associated with an index time. The method may then perform a full backup by storing each message and a backup time associated with the full backup on a backup medium, and perform a partial backup by storing selected messages on the backup medium dependent upon a difference between the index time associated with each message and the backup time. In one embodiment the partial backup may be performed by backing up each message that includes an index time that is dated after the backup time. In a further embodiment, each message on the mail server is contained in a mail folder object, and storing the backup time may comprise modifying a data member of the mail folder object.

Abstract: A microcomputer with a built-in non-volatile semiconductor memory, which can automatically perform a work of temporarily interrupting automatic writing or automatic erase and accepting an interruption process when an interruption occurs during the automatic writing or automatic erase by using an interrupt request signal for a microcomputer as an external input for controlling automatic writing or automatic erase of a flash memory.

Abstract: A semiconductor memory device, comprising a memory array including a plurality of memory cells capable of storing data of at least 1 bit, includes a data write control section for controlling a data write operation to the plurality of memory cells; an address signal generation section for generating an address signal which represents an address of a prescribed memory cell; a determination section for determining whether or not to write data to the prescribed memory cell and outputting a first write signal; a data register section for storing data represented by the first write signal and outputting a second write signal; and a data write section for writing data to the prescribed memory cell based on the second write signal. The data register section stores the data based on a control signal which is output by the data write control section.

Abstract: A memory management system adapted to process linked list data files. The system has a plurality of low storage capacity high speed memories and a lower speed high storage capacity bulk memory. An access flow regulator generates requests for the reading and writing of linked list files by the memories. The head and tail buffers and at any intermediate buffers of a linked list are written into the high speed memories. The intermediate buffers are immediately transferred from the high speed memories to said bulk memory while leaving the head buffer and the tail buffer of the linked list in the high speed memories. In read operations, the head and tail buffers are read from the high speed memories. The intermediate buffers are transferred from the bulk memory to said the high speed memory and then read from the high speed memories.

Abstract: Various embodiments of the invention relate to communicating data between a number of processing elements (PEs) of a signal processor, using a plurality of communication registers (CCRs). For instance, a plurality of the CCRs can be shared by and mapped to the address space of each PE, where each CCR couples a first of the PEs to every other one of the PEs. Moreover, each CCR can include a data payload field and a data valid field to indicate a target PE to read the data in the data payload field. Thus, data can be written to a selected CCR by a PE and stored in the selected CCR to be read by at least one target PE.

Abstract: An apparatus and method for loading a data storage device with a plurality of randomly located data are described. The method includes loading, in response to execution of a multiple data load instruction, data within a destination data storage device wherein one or more data elements from the data are randomly located within a memory device. In one embodiment, addresses of the data elements are contained within a data storage device and indicated as index addresses. In addition, the data elements are stored n one or more data storage areas of a memory device, which include look-up tables, data arrays or the like. In addition, data elements within the destination data storage device, as well as address indexes within the address data storage device may be organized in response to execution of a data shuffle instruction according to a data processing operation instruction.

Abstract: A memory management system adapted to process large data files. The system has a plurality of low storage capacity high speed memories and a lower speed high storage capacity bulk memory. An access flow regulator generates requests for the reading and writing of data files by the memories. Large data files have a first part and an excess portion. Both parts of each file are written into the high speed memories. The excess portion of each file is immediately transferred from the high speed memories to the bulk memory while leaving the first part in the high speed memories. In read operations, the first part is read from the high speed memories. The excess portion is transferred from the bulk memory to the high speed memory in a burst mode and then read from the high speed memories.

Abstract: A non-volatile includes a memory cell array for storing data, a decryption circuit for decrypting data read from the memory cell array using a prescribed computing process, and a decryption control circuit for activating the decryption circuit according to an inputted decryption command during a read operation.

Abstract: A method and system for using XML for both a protocol layer and application data are described. The method comprises the steps of initiating a connection by a client to a server to form a session, responding by said server to said client indicating that said connection has been successfully completed, submitting a request by said client to said server for service, responding by said server to said client by providing said service and terminating the connection by said client. A session is maintained and a plurality of requests for service by a client and a server responds to those requests by providing the requested service or an error message. The session is maintained until all requests made by a client have been serviced and the requests made by a client may be either synchronous or asynchronous. The system comprises a client and a server coupled to said client by a communications link.

Abstract: There is provided an electronic device including: a storage medium in which content data is divided into units of clusters and stored; a link information table that records the link structure of the clusters in the storage medium; a cluster table that records, of the series of clusters constituting the content data stored on the storage medium, the cluster number of clusters at predetermined intervals; and playback means for reading and playing the content data in units of clusters. In playing the content data in reverse, if the cluster number of a target cluster to be read is not recorded in the cluster table, the cluster number of the target cluster is obtained by tracing the link information table from a cluster, of the clusters recorded in the cluster table, previous to the target cluster, and the cluster indicated by the cluster number thus obtained is read.

Abstract: A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the SRAMs so that repeated hits to that bank are cached by reading from the SRAM. In the event of a write to a bank that is being refreshed, the write data are stored in one of the SRAMs. After the refresh of the bank has been completed, the data stored in the SRAM are transferred to the DRAM bank. A subsequent read or write to a second DRAM bank undergoing refresh and occurring during the transfer of data from an SRAM to the DRAM is stored in either the second bank or the other SRAM.

Abstract: A method of operating a digital computer includes the steps of addressing a memory, reading a row of data from the memory, providing the same computational instruction simultaneously to each processor element of a plurality of processor elements, where each of the processor elements is selectively coupled to a corresponding bit position of the memory row of data, performing the same computational operation on a selected plurality of data bits in parallel, and writing the result into the memory at the same row as the data was read from.

Abstract: A method for resynchronizing a primary volume in a primary system and a secondary volume in a secondary system over a network includes, when a network connection between the primary system and the secondary system is interrupted, creating a snapshot of the primary volume and determining data updates transmitted from the primary system to the secondary system that were not acknowledged by the secondary system. The method further comprises, when the network connection is reestablished, determining differences between the snapshot and the primary volume, transmitting the differences and the unacknowledged data updates from the primary system to the secondary system, and updating the secondary volume with the differences and the unacknowledged data, wherein the secondary volume becomes an updated copy of the primary volume.

Abstract: In a storage system comprising multiple storage devices with different interfaces, the characteristics, including the type of interface, of the storage devices on which the source volume is constructed are checked, a volume having the characteristics that match them is selected as the destination volume, and the contents of the source volume are automatically replicated into the destination volume. Candidates for replication (destination) volumes are automatically selected and presented to the user or the administrator, and replication volumes are automatically allocated, without requiring the user or the system administrator to be concerned with the characteristics of the storage devices.

Abstract: A method, system, and computer-readable medium for maintaining up-to-date, consistent backup copies of primary data that are immune to corruption even when security of the primary data is breached. Independent security domains are established for primary and secondary data, such that access to each security domain must be obtained independently of access to the other security domains. For example, a host computer system having access to data storage in the primary security domain does not have access to data storage in the secondary security domain, and vice versa. Changes to primary data are synchronously replicated over a tightly controlled replication link from primary data storage in the primary security domain to secondary data storage in the secondary security domain. A change to the data is completed in the primary security domain when an acknowledgement is received that the change to the data has been stored in secondary data storage.

Abstract: Systems and methods are provided for searching at least one content addressable memory entry associated with a content addressable memory (CAM). A given content addressable memory entry comprises a plurality of CAM fields. At least one input selector controls access to the plurality of CAM fields, such that retrieval of a subset of the plurality of CAM fields is selectively enabled. A match evaluator compares an enabled subset of CAM fields to a search value.

Abstract: A method for selectively inserting cache entries into a cache memory is proposed in which incoming data packets are directed to output links according to address information. The method comprises the following steps: a) an evaluation step for evaluating for each incoming data packet classification information which is relevant to the type of traffic flow or to the traffic priority to which the data packet is associated; b) a selection step for selecting based on the result of the evaluation step whether for the data packet the cache entry is to be inserted into the cache memory; c) an entry step for inserting as the cache entry into the cache memory, in the case the result of the selection step is that the cache entry is to be inserted, for the data packet the address information and associated output link information.

Abstract: A cache structure comprising a plurality of tag arrays and a plurality of data arrays, the tag arrays each configured to point to lines of data in multiple ones of the plurality of data arrays, wherein multiple tag arrays are searched in parallel for data that may be contained in the data arrays.

Abstract: According to some embodiments, a portion of local memory allocated to a thread by a programming statement includes an indication of a read/write status of the portion and symbolically references a buffer name wherein the symbolically referenced buffer name includes both letters and numbers.

Abstract: A structure and associated method of transfer data on a semiconductor device, comprising: a plurality of systems within the semiconductor device. Each system comprises at least one processing device and a local memory structure. Each processing device is electrically coupled to each local memory structure within each system. Each local memory structure is electrically coupled to each of the other said local memory structures. Each local memory structure is adapted to share address space with each of the processing devices. Each processing device is adapted to transmit data and instructions to each local memory structure.