Abstract: Power conservation may be achieved in a front end system by disabling a segment builder unless program flow indicates a sufficient likelihood of segment reuse. Power normally spent in collecting decoded instructions, detecting segment beginning and end conditions and storing instruction segments is conserved by disabling those circuits that perform these functions. An access filter may maintain a running count of the number of times instructions are read from an instruction cache and may enable the segment construction and storage circuits if the running count meets or exceeds a predetermined threshold.

Abstract: When a program is activated, data recorded in a predetermined sector is reproduced by an error correction. When no reproduction error occurs, the data in the predetermined sector is reproduced without conducting the error correction. When reproduced data are not a predetermined pattern, it is determined that write software illegally writes dummy data to the predetermined sector, instead of the predetermined pattern, and an optical disc where the program is activated is a copied optical disc. Accordingly, a process conducted by the program is terminated. Therefore, a process realizing original functions based on the program cannot be executed.

Abstract: A method for managing the access procedure for large block flash memory by employing a page cache block, so as to reduce the occurrence of swap operation is proposed. At least one block of the nonvolatile memory is used as a page cache block. When a host requests to write a data to storage device, the last page of the data is written into one available page of the page cache block by the controller. A block structure is defined in the controller having a data block for storing original data, a writing block for temporary data storage in the access operation, and a page cache block for storing the last one page data to be written.

Abstract: Systems and methods for selecting pin functionality in memory controllers are provided. These memory controllers have pins that can be used to drive different types of signals, depending on the type of memory coupled to the memory controller. For example, pins can be used to drive clock signals or chip select signals. Accordingly, because different types of memory require different numbers of clock and chip select signals, the same memory controller can be advantageously used with different types of memory. Moreover, memory controller pins that would ordinarily go unused with some types of memory can now be used to increase the number of such memories that can be coupled to the memory controller.

Abstract: The present invention provides for a cache-accessing system employing a binary tree with decision nodes. A cache comprising a plurality of sets is provided. A locking or streaming replacement strategy is employed for individual sets of the cache. A replacement management table is also provided. The replacement management table is employable for managing a replacement policy of information associated with the plurality of sets. A pseudo least recently used function is employed to determine the least recently used set of the cache, for such reasons as set replacement. An override signal line is also provided. The override signal is employable to enable an overwrite of a decision node of the binary tree. A value signal is also provided. The value signal is employable to overwrite the decision node of the binary tree.

Abstract: A computer network file system is described. The computer network file system includes first metadata, which is managed primarily by a first file server that is operably connected to a network fabric. The first metadata includes first file location information, and the first file location information includes at least one server id. The computer network file system also includes second metadata, which is managed primarily by a second file server that is operably connected to a network fabric. The second metadata includes second file location information, and the second file location information includes at least one server id. The first metadata and the second metadata are configured to allow a requester to locate files that are stored by the first file server and files that are stored by the second file server in a directory structure that spans the first file server and the second file server.

Abstract: Provided are a method, system, and program for maintaining data in a first cache and second cache, wherein a backup cache maintains a backup copy of data in the first cache, and wherein the first cache is used to cache a first set of data in a storage system and the second cache is used to cache a second set of data in the storage system. An unavailable state of the first cache is detected. In response to detecting the unavailable state, requests to the first set of data are blocked and at least one space in the second cache is allocated for data in the backup cache. Requests to the first set of data are allowed to proceed after the at least one space is allocated in the second cache and before the data in the backup cache is copied to the at least one allocated space in the second cache. The data from the backup cache is copied to the allocated at least one space in the second cache after the requests to the first set of data are allowed to proceed.

Abstract: A method to improve drive read performance in a disc drive includes powering-up a disk drive, reading reassigned sectors data from a reassign spare pool, and storing the reassigned sectors data in a reassigned cache segment. This method also includes initiating a read request, detecting a reassigned sector within the read request, and determining whether the requested sector can be located in the reassignment cache. If the reassigned sectors are found in the cache, then the method includes transferring the reassigned sector data from the reassignment cache to the read buffer or directly to the requesting host computer. If the reassigned sectors are not found in the cache, then the method includes seeking to the reassignment spare pool to fetch as much reassigned sectors data as the reassignment cache can hold. In another embodiment, the reassigned sectors data stored in a reassignment cache segment is located in a buffer.

Abstract: There is provided a method for aligning and inserting data elements into a memory based upon an instruction sequence consisting of one or more alignment instructions and a single store instruction. Given a data item that includes a data element to be stored, the method includes the step of aligning the data element in another memory with respect to a predetermined position in the memory, in response to the one or more alignment instructions. A mask is dynamically generated to enable writing of memory bit lines that correspond to the aligned data element. The memory bit lines are written to the memory under a control of the mask. The generating and writing steps are performed in response to the single store instruction.

Abstract: A memory system employing a directory-based cache coherency scheme comprises a memory unit, a data bus, a plurality of information buses, and a memory controller. The memory unit comprises a plurality of memory modules storing a plurality of cache lines, with each cache line comprising a plurality of data bits and an associated plurality of informational bits. The data bus is coupled to each of the memory modules and is configured to read/write data from/to the memory modules. One information bus of the plurality of information buses is coupled to each of the memory modules and is configured to read/write informational bits to/from the memory modules.

Abstract: A processor card for supporting multiple cache configurations, and a microprocessor for selecting one of the multiple cache configurations is disclosed. The processor card has a first static random access memory mounted on a front side thereof and a second static random access memory mounted on a rear side thereof. The address pins of the memories are aligned. Each pair of aligned address pins are electrically coupled to thereby concurrently receive an address bit signal from the microprocessor. During an initial boot of the microprocessor, the microprocessor includes a multiplexor for providing the address bit signals to the address pins in response to a control signal indicative of a selected cache configuration.

Abstract: A remote site stores data received from a currently-used site and transfers the stored data to a proximal site. The proximal site stores the data received from the remote site and transfers the stored data to the currently-used site. The currently-used site crosschecks the data returned from the proximal site against the data transmitted to the remote site, and when the two data do not match each other, transmits the data to the remote site again.

Abstract: A method for calculating a block cache size for a host process or application on a computer based at least upon virtual memory page evictions and/or virtual memory page reclamations for the computer. A virtual memory page eviction is the act of removing the contents of a physical memory page for the purpose of loading it with the contents of another virtual memory page. A virtual memory page reclamation is the return of a page to a working set that was previously removed by the operating system due to memory constraints. The page must not have been evicted. Additional fundamental properties of the application and the computer may be used, such as available physical memory on the computer, total physical memory, and block evictions. A block eviction is the act of removing the contents of a block from the block cache for the purpose of loading it with new contents.

Abstract: Provided are a method, program, and system for managing data. A mirror policy is processed indicating volumes in a first storage system to mirror to volumes in a second storage system and volumes in the second storage system to mirror to volumes in a third storage system, wherein the third storage system is at a first geographical location remote with respect to a second geographical location including the first and second storage systems. A failure is detected of the first and second storage systems at the first geographical location. Automatic reconfiguration is made to network resources directing I/O requests to volumes in the first storage system to direct I/O requests to volumes in the third storage system.

Abstract: In a memory device with a bank of N memory blocks, an address is generated for a first and a second one of the blocks. The first and second addresses include addresses for current first and second possible “refresh blocks”. If its memory block does not contend with the current first possible refresh block, an externally generated access to one of the N memory blocks is permitted and at least a portion of the refresh block is refreshed during a certain interval. In another aspect, the externally generated access is permitted and at least a portion of the current second possible refresh block is refreshed during the same certain interval if: i) the memory block of the externally generated access contends with the current first possible refresh block and ii) the current first and second possible refresh blocks are different ones of the N memory blocks.

Abstract: A storage device controller includes a channel controller to receive a data input/output request sent from an information processor, a disk controller, and a cache memory. The channel controller includes a communication interface unit for the information processor, a data transfer unit connected via a first bus to the communication interface unit, and a processor connected via a second bus to the data transfer unit. The communication interface unit sends a read command to the data transfer unit for the processor. When the first bus conforms to a first communication protocol, the data transfer unit sends a split response to the communication interface unit. The data transfer unit sends the read command to the processor. The processor sends the split response and readout data corresponding to the read command to the data transfer unit. The data transfer unit receives and sends the readout data to the communication interface unit.

Abstract: A removable memory card detachably mounted to a host device. The memory card includes a non-volatile semiconductor memory in which data recorded in the memory is erased as a block of a predetermined data volume. An interface for inputting/outputting data between the data storage device and said host device, and a controller for controlling file management in the semiconductor memory in response to a command from said host device over said interface is also used. Parameters for recording file management data are stored in a system information storage unit. The controller records the file management data in the semiconductor memory when supplied with an initialization command from said host device.

Abstract: A multi-threaded microprocessor with support for packet header splitting during receive packet processing operations and packet header splicing during transmit packet processing operations, as well as optimized recovery of transmit resources, is presented.

Abstract: Replication of volumes is facilitated by tools which provide and manage a pool of mirror volumes. Primary (or production) volumes containing user provided data are easily mirrored by volumes selected from the pool. User criteria can be provided to limit the selection of candidate volumes for mirroring.

Abstract: A flash memory system is disclosed. The flash memory system includes a flash memory comprising more than one physical block and more than one page, where each page can be in an enabled state, a blank state or a disabled state. In use, a merge control section reads data on an enabled page from a predetermined physical block using a read section, and writes the data onto a blank page using a write section, thereby copying the data on the enabled page onto the blank page. A merge control section then disables the enabled page using a page-disabling section. When the copying of the data from all the enabled pages in the predetermined physical block is finished, the merge control section collectively erases all the data in the physical block using an erase section.