Abstract: A non-volatile storage cell has (a) storage points which are insulated from one another and each having a stack of gates formed, in order, by a first insulant in contact with the substrate, a floating gate, a second insulant and a control gate, a source and a drain formed in substrate on either side of the stack and a channel, whose length is oriented in a direction (x) and (b) conductor lines serving to apply electric signals to the stacks of gates and the drains, the second insulant having, in a plane perpendicular to the surface of the substrate and containing the first direction (x), the shape of an inverted U within which is located the entire floating gate, the control gate also being shaped like an inverted U, without projection and within which is located the entire second insulant.

Abstract: A BiCMOS static random access memory (SRAM) is disclosed, which has first and second stage sense amplifiers. Each column in the memory array is associated with a first stage sense amplifier, and the first stage sense amplifiers are arranged in groups, with each group connected in wired-OR fashion to a pair of local data lines. The column address is used to select one of the first stage sense amplifiers for sensing the state of the memory cell in the selected column. One second stage sense amplifier is associated with each group of first stage sense amplifiers, and the second stage sense amplifier associated with the group containing the selected first stage sense amplifier is selected, according to the most significant bits of the column address. The second stage sense amplifiers are connected to a data-out bus in wired-OR fashion, with the output of the selected second stage sense amplifier driving the data-out bus.

Abstract: A crossbar switch which connects N (N=2.sup.k ; k=0, 1, 2, 3) coarse grain processing elements (rated at 20 million floating point operations per second) to a plurality of memories provides for a parallel processing system free of memory conflicts over a wide range of arithmetic computations (i.e. scalar, vector and matrix). The configuration of the crossbar switch, i.e., the connection between each processing element unit and each parallel memory module, may be changed dynamically on a cycle-by-cycle basis in accordance with the requirements of the algorithm under execution. Although there are certain crossbar usage rules which must be obeyed, the data is mapped over parallel memory such that the processing element units can access and operate on input streams of data in a highly parallel fashion with an effective memory transfer rate and computational throughput power comparable in performance to present-day supercomputers.

Abstract: The present invention provides an ECL EPROM circuit which uses a MOS memory cell. The invention includes a technique for programming the memory cell using MOS voltage levels, and also includes circuitry for reading the memory cell at ECL voltage levels. Thus, the programming and reading paths are split to give the ease of programming and the reprogrammability of MOS EPROM devices combined with the reading speed of PROM devices using ECL voltage levels. In one embodiment, two parallel paths are provided to a memory cell to enable it to separately receive reading and writing (programming) signals. The reading path employs ECL components for reading the cell, while the writing path contains MOS components for programming and verifying the cell. The memory cell itself contains a MOS memory element, an ECL pass element, and a sense element coupling the MOS memory element to the ECL pass element.

Abstract: A register architecture for a computer in which a plurality of banks of general purpose registers are used in the register files. Each of the multiple register banks is dedicated to a different user, with one of the register banks being dedicated to servicing interrupts and another of the register banks being dedicated to the operating system of the computer in which the register architecture is incorporated. Associated with each of the register banks is a smaller register bank of status registers in which information concerning the status of the computer is stored.

Abstract: There are disclosed techniques concerning reading out Bloch lines in a Bloch line memory device, where pairs of Bloch lines are used as an information carrier. The pairs of Bloch lines are transferred to the head portion of a stripe magnetic domain and an inplane magnetic field is applied at the proximity of the head portion of the stripe magnetic domain so that the pairs of Bloch lines are split. In this way only one of the Bloch lines can exist stably at the head portion of the stripe magnetic domain. Then the Bloch lines are transformed into a magnetic bubble domain by making electric current to flow through a hair-pin shaped conductor disposed at the proximity of the head portion of the stripe magnetic domain. This magnetic bubble domain is detected by a magnetic bubble detector.

Abstract: An EPROM includes an on chip circuitry for selecting an alternative chapter mode addressing scheme. By utilizing the chapter addressing mode, a plurality of devices can be coupled in parallel, wherein each device is treated as a chapter of the total memory capacity. Hard latches are used to store a designated code and soft latches are used to latch in chapter addresses from data lines. A chapter is evaluated if values stored in the hard latch match the values inputted to the soft latch.

Abstract: A Bloch line read/write memory in which a Bloch line or lines near the end portion of a stripe domain are moved in a predetermined direction to turn the direction of a wall magnetization at the end portion to a right turn direction as viewed form the surface of a film on which a bubble chopping conductor is disposed, and thereby reduce erroneous reading errors and increase the chopping current margin.

Abstract: A non-volatile memory provides a signal hold circuit which uses a FAMOS instead of an input transistor of a ratiod inverting amplifier and outputs a change in a threshold value of the FAMOS, for the purpose of reducing the number of elements of the signal hold circuit. FAMOSs for programming and latching are provided respectively, and the FAMOSs are interconnected to each other at their floating gate electrodes to isolate the signal hold circuit and a program circuit and hence prevent a DC current path from being formed between those two circuits, for the purpose of miniaturization of a memory cell.

Abstract: A dual-port memory which features a pipelined serial port is disclosed. The serial side of the dual-port memory contains a ripple counter which is broken between predetermined stages. The contents of the stages above the break are decoded to select a group of bits of the serial register for output, and the contents latched in a latch. In serial output, the contents of the stages below the break are decoded, so that responsive to the stages below the break reaching a certain value, the stages above the break are incremented and the incremented value decoded. Pass transistors between the register and the latch are turned off during such time as the incremented value is being decoded, so that the new value will not disturb the output. The latched output is selectively presented by a multiplexer which selects the latch bits responsive to the value of the stages below the break. Upon the value of the stages reaching its minimum value (i.e.

Abstract: A CMOS-RAM memory is composed of at least one main memory area SF whose memory cells are realized with a seven transistor basic cell (SC) in a gate array arrangement. The memory cells are thereby arranged in a matrix in the main memory area. A word line decoder (WD) lies at one side of the main memory area (SF) of the gate array arrangement in row direction, this word line decoder (WD) containing - per row of memory cells-a decoder sub-circuit (WDT) realized with basic cells for generating a word line signal from address signals. A drive circuit (AST) is arranged between the word line decoder (WD) and the main memory area (SF), the drive circuit (AST) providing - per row of memory cells - a drive sub-circuit (ASTT) for generating a write signal in inverted and non-inverted form from the word line signal and from a selection signal with which the memory cells of a row of memory cells are driven.

Abstract: A memory array layout using complementary bitlines connected to a single sense amplifier. Extending from the sense amplifier, bitlines which are unconnected are extended to the middle of the array. One complementary bitline is then connected to a series of memory cells extending away from the sense amplifier. The other complementary bitline loops back and is connected to a set of memory cells extending back toward the sense amplifier. The first bitline section extending from the sense amplifier may be advantageously formed in a metal layer above the substrate thereby occupying no space in the substrate itself. All noise generated on the first sections of the bitlines will be canceled by the complementary parallel structure of the bitlines. Because the second sections of the bitlines are laterally separated, a wordline passing across each of the second sections addresses a singel memory cell. Therefore an optimally compact cross-point memory array may be fabricated.

Abstract: An intelligent electrically erasable, programmable read-only memory achieves improved worst-case read operation latency by allowing for the interruption of write operations by subsequently received read requests. In the preferred embodiment, a state machine controller executes write operations by an iterative process of write pulses and write verify cycles. In addition, cells are erased prior to being written to by a similar iterative process. Both the write operations and the erase operations may be interrupted by read requests received after the write operation has begun execution. To avoid reading incorrect data in the case of a read operation at the same address as an interrupted write operation, a comparator matches read operation addresses with latched write operation addresses and provides the read operation data from a write data latch in the case of a match.

Abstract: A static RAM includes a plurality of chips. The chips each comprise a plurality of memory cells for storing data, column-selecting transistors, bit-lines to which the plurality of memory cells and the column-selecting transistors are connected, and a voltage control circuit which can adjust the electrical potential of the bit-lines so as to allow the column-selecting transistors to operate when selecting one of the chips. By use of the voltage control circuit, the static RAM can operate at a high speed when not only address selecting operation but also chip selecting operation is required.

Abstract: A static RAM includes test features which provide for the detection of soft defects which may cause a defective SRAM cell to behave as a functional DRAM cell. Provision is made for writing either a high or a low logic state to each bit line of the SRAM while not writing any value to its complementary bit line and for sensing the state of each bit line independently of the state of its complementary bit line. In addition, a current test is provided which detects soft defects by means of the increased inverter leakage current caused thereby. It is possible, by properly combining these tests, to reliably detect all soft defects, thereby assuring the data retention capability of the SRAM. This technique avoids the long hold time and/or high temperature test techniques used in the prior art.

Abstract: In a non-volatile semiconductor memory of this invention, a memory cell array constituted by a plurality of memory cells is divided into a plurlaity of blocks, and erase lines which are common to the respective blocks and independent from each other are arranged. In the data write mode, a predetermined voltage is applied to only the erase line connected to a selected one of the blocks.

Abstract: A read only memory in which a portion of an address area thereof is allotted to that of another memory. The read only memory comprises at least one address decoding output circuit with a read only memory portion. The address decoding output circuit is formed to be programmable at the same time as the read only memory portion. Thus, an apparatus having this read only memory can be miniaturized and have a low power consumption, and the process of producing a system including this read only memory is simplified.

Abstract: An optical memory circuit comprises two photodetectors, and an intermediate signal conductor for connecting the two photodetectors, wherein the two photodetectors and the signal conductor are connected in series in a closed circuit, wherein each of the photodetectors comprises two spaced Schottky electrodes symmetrically disposed on a semiconductor substrate and the signal conductor has a capacitance with a time constant of a potential of the signal conductor such that charges are stored in the signal conductor when an optical write signal is incident on one photodetector and stored charges are released from the signal conductor when an optical read signal is incident on the other photodetector.

Abstract: Modified CAMs are used to generate a reset signal to other redundant CAMs which provide decoding for accessing redundant memory. Because the redundant CAMs use a single UPROM, half-latch circuit, the redundant CAMs are capable of latching to the wrong logic state. Whenever signal conditions which can cause improper latch-up are present, at least one of the modified CAMs are affected due to their sensitivity. Then, the modified CAMs will generate a reset signal until the improper latch-up condition is removed.

Abstract: A CMOS sense amplifier for a dynamic read/write memory employs a latch circuit with cross-coupled N-channel transistors and cross-coupled P-channel transistors, returned to the voltage supply and ground through P and N channel transistors selectively activated by sense clocks. Differential inputs of the sense amplifier are connected to the bit lines. The N-channel transistors are employed for initial sensing, and then both N-channel and P-channel transistors in sequential order for amplification and restoring the I-level. This results in better balance, and smaller N and P channel latch transistors may be used, saving area, saving power and increasing speed.