Abstract: A read amplifier formed of a load component (L), a differential amplifier component (DIFF), a compensation transistor (N6), a switching transistor (P1) connected between a supply voltage (V.sub.DD) and the load component (L). The pre-loading potential of the read amplifier at its outputs LA, LA is about 2.5 volts. During the pre-loading phase, the two supply voltages (V.sub.DD, V.sub.22 =ground) are disconnected and the pre-loading potential is established by compensation of capacitances at the outputs LA, LA which results in an improved read amplifier.

Abstract: In a method for programming an antifuse element which includes a pair of conductive electrodes separated by an insulating layer a predetermined number of voltage pulses are first applied across the electrodes of the antifuse and the current drawn by the antifuse is simultaneously measured. When the measured current indicates that the antifuse dielectric has ruptured, a second step includes continuing to apply pulses and calculating the difference in current sensed between successive measurements. In a third step, a predetermined number of additional pulses are applied after the difference in current between successive pulses falls below a predetermined threshold. In a fourth step, an additional predetermined number of pulses are applied and the current drawn at the end of the sequence is measured. If it is greater than the current drawn at the beginning of the sequence by a predetermined threshold, the third step is repeated. If not, the programming process ends.

Abstract: An apparatus for reading out information written on a magneto-optical data storage medium through magnetization thereof in one of opposite directions normal to a surface of the medium, comprising a device for emitting circularly or linearly polarized light to the storage medium in a direction parallel to the direction of magnetization of the storage medium, and a device for readng out the information based on a change in total quantity of the polarized light which is reflected from the storage medium or transmitted through the medium. The apparatus may comprise at least one polarizing beam splitter and a quarter-wave retardation plate. The device for reading out the information may comprise at least one data-reading optical detector which generates a signal corresponding to the detected total quantity of the light reflected from the storage medium.

Abstract: A data protection system for protecting data stored in a memory in a data processing system having at least a channel system, a device controller and an external storage device. The data protection system includes a memory provided in the device controller which receives a power source voltage, and temporarily stores data to be transferred. A battery is connected to the power source and the memory, is charged by the power source when the power source is normal, and supplies a battery voltage to the memory when the power source is accidentally interrupted. A first voltage check circuit is connected to the battery, compares the battery voltage with a first reference voltage, and generates a battery error signal when the battery voltage is lower than the first reference voltage.

Abstract: An EEPROM device provides increased speed and less susceptibility to soft writes during reading and programming operations. A unique circuit design and operating method obviates the need for applying a high programming or erase voltage in the path between the memory array and sense amplifier. Such high programming and erase voltages are applied, as needed, directly to the memory array, thereby allowing all transistors which carry signals from the memory array to the sense amplifier to be fabricated as low voltage devices, thereby increasing their speed of operation and thus the speed of operation of the memory device as a whole. By applying the relatively high programming and erase voltages to the source of the memory transistors, and reading from the drain of the memory transistors, the source and drain as well as associated circuitry are fabricated to optimize their intended functions.

Abstract: The present invention utilizes bypass circuitry to shorten the cycle time of a cache memory by shortening the time required to perform a write through read operation (WTR). The bypass circuitry senses when a WTR operation will occur by comparing the encoded read and write addresses to determine when the encoded addresses are equal. When the encoded addresses are equal, a WTR operation is requested and the bypass circuitry sends the data to be written into memory to both the write address location and the cache output buffer. The bypass circuitry does not wait to access the data from the memory cells through the read decode, rather, it directly sends the data to the output buffer. The bypass circuitry provides a parallel read and write operations instead of serial operations during a WTR, thereby shortening the machine cycle time.

Abstract: In a selecting circuit for a memory operating mode, the circuit has a mode enable pulse generator which produces a short pulse for a mode enable pulse. A mode selecting clock generator which receives a mode enable pulse and selects a memory operating mode. The number of the mode selecting clock generator is determined by the number of memory operating mode to be used. A fuse, coupled with each of the mode selecting clock generators, is out when the corresponding mode selecting generator is selected and hence produces a mode selecting signal.

Abstract: A data transfer circuit is connected between first and second circuits so as to control data transfers therebetween. The data transfer circuit comprises first and second latch circuits for latching data in response to first and second latch control signals, respectively, a first data transfer gate connected between the first circuit and the first latch circuit and responsive to a first gate control signal to make electrical connection or disconnection therebetween, a second transfer gate connected between the first and second data latch circuits and responsive to a second gate control signal to make electrical connection or disconnection therebetween, and a third data transfer gate connected between the second data latch circuit and the second circuit and responsive to a third gate control signal to make electrical connection or disconnection therebetween.

Abstract: An improved semiconductor memory device in which serial read operations and serial write operations can be performed simultaneously is disclosed. The memory device comprises a memory array of memory cells, a random access port for accessing a desired one of memory cell in the array, a serial read circuit for sequentially reading data from the selected row one by one and a serial write circuit for operatively writing data sequentially applied to the selected row.

Abstract: An improved method for refreshing dynamic random access memory devices is disclosed. Normal refresh clocking signals are monitored and a count accumulated up to a selected value. Refresh operations are then initiated less frequently and only when the selected count has been accumulated. Once control of the bus to the memory has been achieved, a burst of refresh operations are performed prior to release of the bus. Improved efficiency and operating speed may be achieved by minimizing wasted time associated with acquisition and control of the bus. A preferred embodiment illustrates savings associated with a burst of four refresh operations each time the bus to the memory device is acquired for refreshing. Page addressing techniques are enhanced by forcing a change of state of the row address strobe line bus frequently than typical refresh operations.

Abstract: A semiconductor memory device of the type having a pair of transfer gates between a bit line pair and an interconnection pair coupled to a sense amplifier circuit operates at a high speed because of the reduction of parasitic capacitances coupled to the sense amplifier circuit, however, the sense amplifier circuit is so sensitive to an electrical unbalance between the input nodes thereof that a transfer signal line is coupled to the gate electrodes of the transfer gates through a contact window located in such a manner that coupling capacitances between the transfer signal line and the interconnections do not provide the electrical unbalance, then the contact window is by way of example located between the interconnections.

Abstract: For decreasing a semiconductor chip where a semiconductor memory device is fabricated, a memory cell unit and a diagnostic unit are coupled to an output buffer unit through a single data path, and an auxiliary gate control unit is provided in association with the output buffer unit for shifting an output data pin between a high level, a low level and a high impedance state, in which the diagnostic unit checks a plurality of data bits from the memory cell unit to see whether or not the data bits are consistent with one another for producing a first diagnostic signal of either high or low level in a basic testing function but for producing second and third diagnosis signals for shifting the output data pin between the high and low levels and a high impedance state, in which the auxiliary gate control unit steers the output buffer unit in response to the first diagnosis signal or the third diagnosis signal on the single data path but the second diagnosis signal causes the auxiliary gate control unit to steer the

Abstract: During a data-clearing operation, while maintaining in the OFF state the transfer gate transistors in each of the static type memory cells associated with at least one column, the source of one of two drive transistors incorporated in the memory cell is set to a high potential level, and the source of the other drive transistor to a low level. As a result, the clearing operation is performed to a minimum of 1 column in the memory cell matrix. Due to the arrangement of the memory device, no address-selecting operation is required for selecting a memory cell during the clearing operation. Moreover, the clearing operation is carried out in a minimum unit of 1 column in the memory cell matrix. Consequently, the processing time for the clearing operation is reduced. Furthermore, the DC current flowing during the clearing operation is reduced, since the transfer gate transistor in the memory cell is maintained in the OFF state during the clearing operation, with the result that the power consumption is lowered.

Abstract: A single-ended sense amplifier, for fast sensing from a precharged low condition, is provided. In the precharge mode, the amplifier discharges the sensing node to ground, and charges a bias node to a first predetermined voltage. This bias node modulates the current drive capabilities of the first and second charge transistors. Once the sense amplifier enters the sensing mode, the voltage at the bias node causes the first charge transistor to rapidly supply a substantial amount of current to the sensing node. If the selected memory cell is in the conducting state, the voltage at the sense node is discharged to ground and the amplifier output is a low-voltage, indicating the detection of a logic "0" state. Conversely, if the selected memory cell is in a non-conducting state, the voltage at the sense node increases beyond a second predetermined voltage, and the amplifier output is a high-voltage, indicating the detection of a logic "1".

Abstract: A memory capacity detecting device for memory cards including at least one memory chip of a predetermined memory capacity comprises an address specifying section for generating an address signal which selectively specifies two memory chips, a data write-in section for writing two items of preset data into top memory locations of the specified memory chips, and chip number detecting section for detecting the number of memory chips in the memory card by first reading out the data from the top memory location of each specified memory chip, comparing the readout data with the corresponding preset data, and determining the number of memory chips based on the comparision results.

Abstract: A semiconductor memory device includes a memory cell array having a plurality of memory cells and first, second, third and fourth data transferring portions. Tag information, key information and operand data applied to the first data transferring portion are sequentially transferred to the second data transferring portion, the third data transferring portion and the fourth data transferring portion. Any of the memory cells in the memory cell array are selected based on the key information, so that new tag information and operand data are read out from the selected memory cells. The inputted tag information and the tag information read out from the memory cell array are compared with each other by the comparison determining portion. When the information coincides with each other, the inputted key information, the new tag information, the new operand data and the inputted operand data are outputted to the exterior.

Abstract: In a dynamic random access semiconductor memory device comprising a sense amplifier and two pairs of bit lines sharing the sense amplifiers, each of the bit lines having a plurality of memory cells connected thereto, when a memory cell connected to one of the bit-line pairs is selected, the memory cells connected to the other bit-line pair are not connected to the sense amplifier, and, during a refresh cycle for rewriting data into a selected memory cell connected to a bit line of one of the bit-line pairs, the bit lines of the other bit-line pair are disconnected from the sense amplifier.

Abstract: A folded bitline dynamic RAM circuit with reduced shared supply voltages comprised of circuitry for applying full logic high and low supply voltages to respective bitlines during successive active cycles of the RAM circuit, and circuitry for applying reduced supply voltages to the bitlines during successive precharge cycles. By applying reduced supply voltages to the bitlines during the precharge cycles voltage stress on cell access transistors and sense amplifiers of the RAM circuit are reduced. The time required to share the charge residing on the bitline halves at the start of the active cycle is also reduced.

Abstract: An associative data processor including a spin glass type amorphous magnetic film has input areas, output areas, and "hidden" or associative areas. A coil provides selective magnetic biasing, and lasers provide selective digital input to the input and output areas, which are intercoupled by the associative areas. Following input of a number of digital patterns to the processor, and "learning" by heating the associative areas, an incomplete input pattern may be applied, and the complete pattern read by sensing the polarization of reflected polarized light from the output areas.

Abstract: The described embodiment of the present invention utilizes the regular nature of a large number of arrays by providing a grid scheme in the array to provide a low impedance point to point interconnection. In the described embodiment of the present invention a DRAM includes a number of leads running perpendicular to the sense amplifier layout. For a given signal, each lead is interconnected at a bus lead running parallel to the layout of the sense amplifiers. Thus each lead in the parallel array carries a portion of the current. In addition, in this scheme it can be assured that a substantial number of leads will be near any particular sense amplifier which is drawing on the signal provided on the grid array scheme. Because of the close proximity of the parallel conductors, the bus lines to the sense amplifiers need not be as wide as feeder lines in the prior art.