Abstract: A design is disclosed for a cellular computer consisting of many processors, of two kinds, connected in the form of a tree. The computer is intended for the highly parallel execution of programs written in an applicative programming language. The program is stored in the leaf cells of the tree. The computer uses the syntactic structure of the program to guide the embedding of a network of "syntactic nodes" in the tree of machine cells, and execution of the program is accomplished through operations performed by the embedded network of nodes. This computer can execute many user programs simultaneously, it can take advantage of all the parallelism expressed in each user program (storage space permitting), and it can perform in parallel many operations below the level expressed in the user programs.

Abstract: A digital computer system having a memory system organized into objects for storing data and a processor for processing data in response to instructions. An object identifier is associated with each object. The memory system responds to logical addresses for data which specify the object containing the data and the offset of the data in the object. The objects include procedure objects and data objects. The procedure objects contain procedures including the instructions. Each instruction contains an operation code which belongs to one of several sets of operation codes. All instructions in a single procedure belong to a single operation code set, and associated with each procedure is an operation code set identifier specifying the operation code set to which the instructions in the procedure belongs.

Abstract: The invention provides a digital data processor which has been systemetized down to bit level. The processor includes a regular array of identical processing cells which perform a logic operation on incoming bits. The cells repeatedly perform a cell operation under the control of clocks which govern the inputting to and outputting from the cell of data bits. Each bit takes part in a maximum of one cell operation in one repetition of the clock having the highest repetition frequency.Processing cell arrays for dealing with larger numbers may be readily built up from smaller arrays used for smaller numbers.Having obtained a fully working design for one type of processing cell, the full array consisting of a plurality of cells is proven.

Abstract: An information processing system has a bus for providing information transmission, which is received at an external terminal. An input/output circuit is coupled between the bus and the external terminal for effecting the information transmission therebetween. A first control signal controls the timing of the input/output circuit so that the information may be transmitted from the bus to the external terminal. A second control signal controls the timing of the input/output means so that the information may be transmitted to the bus. A third control signal has a timing which is different from both the first and the second control signals so that the information may be transmitted through the input/output circuit. Timing control means selectively applies the first or second control signal and then the input/output circuit operates in accordance with the third control signal.

Abstract: A data processing device fabricated on a single semiconductor substrate including nonvolatile memory for the storage of data and instructions, a central processing unit for performing operations on the data, both connected to an information transfer bus to transfer addresses, instructions and data between the memory and the central processing unit. Further included is an external interface connected to the information bus for providing information on the information bus to external devices. Security bits are also provided for designating the security status of information stored in the memory. Address logic is provided that is connected to the information bus to determine when information in the memory is being accessed. An external interface inhibit logic circuit is provided that is connected to the security bit and the address logic to selectively inhibit the operation of the external interface.

Abstract: A data processing system for supporting a virtual memory is disclosed. Prior to the start of main memory write operation, a processor checks to see if a store buffer has a vacant area to store data to be written into a main memory to execute a current instruction. If a page fault occurs during the main memory write operation, the processor continues to store the subsequent write data for the current instruction and the corresponding virtual or logical addresses in the store buffer to complete execution of the current instruction.

Abstract: An apparatus for controlling the writing of data from a processor into a memory having different read and write times, wherein the memory is connected directly to the processor through address and data buses without the use of an input/output port. A timer circuit is connected to the buses and memory and is controlled by the processor to produce a write timing signal which controls the writing of data into the memory. The processor is placed in a holding state, based on the write timing signal, for a period long enough to assure that the data will be written into the memory in its entirety.

Abstract: An information system for storing and automatically retrieving selected information and transmitting it to a user over a telephone line is described. The system includes a recorder unit on which a series of information messages can be recorded on a recording medium and replayed from the recording medium. A telephone coupler unit for connection to a telephone line detects incoming calls on the line. An automatic controller operates the coupler unit to connect calls through an audio switch assembly to the recorder unit. The controller monitors connected calls to detect touch tone signals from a user and automatically operates the recorder unit in response to the signals to drive it to a user chosen position represented by the signals and to play the message recorded at that position.

Abstract: A beverage vending machine makes use of a microcomputer to compute the time duration for supply of component materials in accordance with stored data and supplied input data.

Abstract: A data processing system which include a central processing unit having a program counter, a main memory for storing a return instruction including the contents of the program counter and interrupting inhibiting information and for storing the contents of a general register in the CPU, interruption means for controlling the storage of the return instruction and the general register contents in the main memory upon occurrence of a first interruption, detection means for reading the return instruction stored in the main memory upon completion of the first interruption and for initiating the immediate occurrence of a second interruption in accordance with the inhibiting information of the return instruction read in the main memory, and return means for restoring the return instruction and the general register contents stored in the main memory to the central processing unit in the event that the detecting means determines that there is no further interruption to be accepted.

Abstract: An interface control system between a plurality of devices, such as a channel and an I/O device, includes sampling means for high speed sampling input control signals on an interface, a compare circuit for comparing a current sampled value sampled by the sampling means with an expected value for the input control signal previously prepared in the system and with a previously sampled value, respectively, to produce a compare equal signal when the sampled value is equal to the expected value, a matrix logic circuit responsive to the compare equal signal to set an output signal line corresponding to the expected value and an expected value for next sampling, and a circuit to produce a signal indicating an error condition or an exceptional condition when the sampled value is not equal to the expected value and the previous sampled value, to activate another logic circuit.

Abstract: A data communication system including reflectors having first light emitting elements for radiating light and first light receiving elements for receiving light, a plurality of transceivers disposed confronting said reflectors and having second light emitting elements for radiating light and second light receiving elements for receiving light, and a data processing unit to be connected to the transceivers, wherein light corresponding to the data to be transmitted from the data processing unit is converged and radiated from the second light emitting element of the transceiver to the reflector, the light from the transceiver is received by the first light receiving element of the reflector, light corresponding to the data thus received is radiated from the light emitting element of the reflector to all of the transceivers confronting said reflector and is received by the second light receiving elements of the transceivers, and the data thus received is sent to the data processing unit.

Abstract: A bus system architecture and method provides on a substrate a bus line system for first and second circuit boards designed to extend across the substrate. Individually dedicated first, second and third bus lines for the first circuit boards are provided in a first bus line array at one side of the substrate. Individually dedicated fourth, fifth and sixth bus lines for the second circuit boards corresponding, respectively, to the first, second and third bus lines, are provided in a second bus line array representing a mirror image of the first bus line array at an opposite side of the substrate. An area of the substrate between the first and second bus line arrays may be subdivided into sequential first and second regions adjacent the first bus line array, and sequential third and forth regions adjacent the second bus line array. A third bus line array is located in the first region for the first circuit board, and a fourth bus line array in the fourth region for the second circuit boards.

Abstract: An interactive terminal system includes a high speed link controller (HSLC) and a number of work stations, all coupled in common to a single conductor coaxial bus. The HSLC includes apparatus controlled by a microprocessor to put the HSLC in a wraparound test mode. The microprocessor transfers test bytes which pass through the HSLC logic and are checked by the microprocessor.

Abstract: System and method for controlling the transfer of data between a plurality of processors in a network. Synchronization between the processors is effected by means of asynchronously operated address counters which control the transmission of data from the processors. When a transmission occurs, the address counters are all set to a count corresponding to the address of the transmitting station, and in the event of a transmission from more than one processor, the address counters are reset to an initializing level. A station is permitted to transmit only when the count in its address counter corresponds to the address of the station.

Abstract: Substitution of a general purpose data processing system for special purpose magnetic tape recording equipment, in certain existing network environments--one example being present telephone call billing networks--offers advantages in respect to equipment costs and data handling efficiency, but requires presently disclosed adaptation for effecting the substitution efficiently and with complete transparency to unaltered parts of the environmental (host) network. While simulating a data recording operation the substituted system receives an arbitrary length train of data bytes clocked at a first rate followed by a cyclic redundancy check (CRC) byte timed at a slower second rate. In order to maintain network transparency, the substituted system must retransmit the data and CRC check bytes, in their received order and at their respective reception rates, after a delay associated with the physical separation between recording and reproducing heads in the "native" tape recording equipment.

Abstract: A system for resolving the contention between the central processing unit (CPU) and the cathode ray tube (CRT) controller in accessing the video memory array, or video random access memory (RAM), of a data processing system is disclosed. The conventional CPU-CRT controller accessing sequence is modified to provide a CPU access period between successive CRT controller access periods. In addition, arbitration logic is included to provide CRT controller access priority when there is contention between the CPU and the CRT controller. By thus assigning video memory access priority to the CRT controller and increasing the length of the video memory array "read" time during which video information is provided to the system's display device, video display performance is enhanced and display degradation due to video memory array operating speed limitations is essentially eliminated.

Abstract: The Array Processor of the present invention is comprised of a plurality of modular Elemental Processors, the modules being of a number of different functional types. These modules are associated so that the Elemental Processors are architecturally parallel to one another. The principal flow of data within the Array Processor, based on the simultaneous transfer of data words within the Elemental Processors, is thereby correspondingly parallel. The modules are also architecturally associated as functional planes that lie transverse to the Elemental Processors. Each functional plane is thereby comprised of an array of modules that are each otherwise associated with a separate Elemental Processor. Further, the modules of a given functional plane are of a single functional type. This allows the data of a two-dimensionally structured data set, present within the Array Processor, to be processed identically and in parallel by a common logical operation as provided and performed by a functional plane.

Abstract: A programmable controller has eight I/O buses which will support a corresponding number of I/O modules. The I/O capacity of the programmable controller may be increased by replacing four of the I/O modules with an I/O address module and three I/O interface modules that drive I/O expansion buses. Up to eight I/O racks, each containing three I/O modules and one adaptor circuit, can be connected to the I/O expansion buses.

Abstract: The invention relates to a multi-microcomputer system employing a direct memory access controller for direct memory access. The data buses and address buses of the several microcomputers are interconnected by means of bus separator stages which normally isolate the buses, but enable the buses to communicate with each other during data exchange between the read-write stores of the individual microcomputers. The microprocessors are switched into their HOLD state during data exchange, and the data exchange is effected via the DMA controller which is supplied with the address zones of the source and destination by a designated microcomputer. In order to increase operational reliability, two or more multi-microcomputer systems, each containing a DMA controller, can be connected in parallel.