Abstract: A method of initializing non-synchronous peer-to-peer data communication rings, and for effecting error recovery in such networks. On detection of error, each station operates in a purging configuration to clear the ring. In the purging configuration the station's receiving circuits are isolated and its transmitting circuits transmit "clear" signals containing this station's own address as destination. These signals serve to purge all potentially erroneous information in all upstream stations which then are operationally connected to that station. If a loss condition is persistent the station operates first in a "bypass" configuration for a third predetermined time interval, then in the purging configuration for the second time interval, and then resumes normal operation. In the bypass configuration the station's ring input is connected directly to its output and the (locally clocked) output of its transmitting circuits is connected to the input of its receiving circuits.

Abstract: A central dictation and transcribing system including a plurality of dictate stations (16) and a plurality of transcribe stations (17) in which recorded dictation is recorded in the form of digitized samples. A plurality of selectively operable controls (38, 39, 40, 41, 42, 43, 45, 46) are used to rearrange the reproduced order of dictation heard by the transcriber by inserting, deleting, and moving segments of previously recorded dictation. All final dictation heard by the transcriber is continuous and in an order determined by operation of the controls. The structure includes memory (11, 12) for storing the digitized samples and a map memory (40) for storing a plurality of address pairs (127, 128) indicative of when normal sequential reproduction of digitized samples from the main memory is to be altered. A predetermined jump code (98) is stored at each location in the main memory to indicate that a change of sequence is to be made from that address and reference to the map memory should be made.

Abstract: Image rotate control circuitry buffers one column of display or video data which is subsequently printed along a horizontal print line. A video dot counter cycles each horizontal scan line while a print line counter cycles each vertical scan. Video data is entered into the buffer when the count in the video dot counter equals the count in the print line counter. After one refresh of the display the buffer contains one print line of data. This data is shifted from the buffer to the printer during the vertical retrace or vertical blank period of the display. The control circuitry sends a strobe signal to the printer for the print operation as a new column of data is being buffered during the next refresh of the display.

Abstract: A system for controlling the flow of data over a common bus between a plurality of processing units is disclosed which preferably includes a MOS/LSI circuit controller chip associated with each processing unit for awarding priority of access to the common bus when two or more processing units attempt to simultaneously gain access to the common bus. A contention circuit located in each controller chip is responsive to the sensing of each bit in the address of its associated processing unit, and generates a plurality of transitions on the common bus during the time a binary one bit is sensed in the address and listens for the presence of any transition on the common bus during the time a binary zero is sensed in the address. Access to the common bus is lost when transitions are detected on the bus during the time a binary zero bit is sensed and acquired when no transitions have been detected at the completion of the sensing of the address of the requesting processing unit.

Abstract: The directory and cache store of a multilevel set associative cache system are organized in levels of memory locations. Round robin replacement apparatus is used to identify in which one of the multilevels information is to be replaced. The directory includes parity detection apparatus for detecting errors in the addresses being written in the directory during a cache memory cycle of operation. Control apparatus combines such parity errors with signals indicative of directory hits to produce invalid hit detection signals. The control apparatus in response to the occurrence of a first invalid hit detection signal conditions the round robin apparatus as well as other portions of the cache system to limit cache operation to those sections whose levels are error free thereby gracefully degrading cache operation.

Abstract: A keyboard-programmable electronic computer utilizes a user-accessible table located in memory to allow the user to list memory addresses to be associated with various key codes corresponding to keys on the keyboard. When a key is depressed upon the keyboard, the computer checks the table for the corresponding key code and, if it is listed therein, the user-written subroutine located in memory at the address associated with the key code is performed. The user-written subroutine has the capability of utilizing both the events of key depression and the status of continued key depressions as program variables.

Abstract: The storage locations of a memory system map a field of sample points. Apparatus affording parallel access to a plurality of storage locations describing an array of the sample points in an access window, which window can be shifted to any selected region of field of sample points responsive to orthogonal address coordinates of one of the sample points in the array, is described.

Abstract: A mechanism is provided for saving substantial time when a service processor needs to communicate with one of a plurality of satellite devices, but does not know the identity of the specific device. The service processor, through an intermediate adapter, issues a command which addresses the class of devices. The adapter redirects the command to the specific device, and concatenates the response from that device along with the device's identity and forwards this to the service processor. Further communication between the service processor and the specific device can then take place directly.

Abstract: Multiprocessing systems having changeable CPU configurations generate unique changeable identifications (ID's). These are presented by I/O channels over various I/O connection paths, in association with special path defining commands and function data. Related path state indications are stored peripherally in path map tables and define path group associations for sustaining path-independent I/O operations. When a device is reserved via one path in a path group the reserve affiliation is extended automatically (in the path tables ) to each path in the group, thereby rendering each path accessible in a reserved mode. The path defining commands are used for adding paths to, resigning paths from and disbanding groups. Special sensing commands are used for sensing path reservation and grouping states. When a command for adding or resigning a path is presented to a reserved device via one path in a group the reserve is automatically realigned to the enlarged or reduced group.

Abstract: In order to keep the number of data transfers small in storing bit pattern fields in an external memory, only the first line and the changed data of the bit pattern field are transmitted and the field is reconstructed line by line by means of an interim register and then stored. For this purpose the interim register has, besides a data input connected with the bit pattern field and an input for a STROBE signal, an input for addressing register locations corresponding to those memory building blocks, the data of which has changed from line to line. Advantageously, groups of eight memory building blocks, to which an interim register in the form of an 8-bit decoder register is assigned, are used.

Abstract: An automated system for vending airline tickets to credit card purchasers based upon reservation data stored in a central host computer, without the intervention of any ticket agents. A plurality of remote ticket terminals each include a credit card reader, video monitor, ticket printer, local computer, and an interface for permitting communication with the host computer. The local computer of each terminal reads data from an inserted credit card and causes the video monitor to display alphanumeric and graphic inquiries to the purchaser regarding the passenger's reservation. The CRT of the video monitor is provided with touch input mechanisms for enabling the passenger to respond to the inquiries by placing a finger on a visual response target. The local computer interrogates the host computer to determine the purchaser's reservation data and displays the reservation data on the CRT for confirmation by the purchaser.

Abstract: A microprogrammed commercial instruction processor in a data processing system includes a bank of switches coupled to a multitapped delay line for selecting delay line signals for setting the basic clock timing. Another of the switches when activated conditions the commercial instruction processor so that when it is reset a special clock setting firmware loop is entered. The loop provides an uninterrupted succession of clock pulses which allows one to adjust the basic clock timing within specification.

Abstract: A data communication system which includes a data distributor, a communication station and a plurality of front-end-processors. These front-end-processors are connected with a computer through a common bus. The distributor distributes the data received by the station to one available front-end-processor, which preprocesses the received data, and transfers the pre-processed data to the computer through the bus. By operating the front-end-processors in parallel with respect to successively received packets of data, the processing speed of the system is increased.

Abstract: A numerical control system executes part programs which contain parameters and arithmetic expressions containing parameters. A parameter table containing parameter values is employed to evaluate parameters and arithmetic expressions during the execution of a part program, and means is provided which enables parameter values to be changed by part program instructions or manual data entry. Macroprograms, such as canned cycles, are stored in the numerical control system in a generalized form in which their instructions contain parameters and arithmetic expressions in lieu of constants. Prior to calling such a macroprogram, the part program assigns suitable values to the parameters employed in the macroprogram.

Abstract: A supervisory control system for interrogating a large number of remote units. A pseudorandom sequence of bits are generated by central control in cycles and received by the remote units. Each remote unit is provided with a pseudorandom bit sequence generator. Upon coincidence of the pseudorandom bit sequence from the central control and the remote unit and upon detection of the address of remote unit and of the specific point in that remote unit, the remote unit sends back to the central control the status information of the selected point during the next succeeding bit time interval. In this manner the statuses of entire set of remote units are interrogated and reported. In accordance with a further aspect of the present control system, the control system commands the remote units for action and the remote units send back command acknowledge signals.

Abstract: A narrow band digital filter is disclosed for rejecting all undesired frequencies, providing a binary signal indicative of when the input frequency is within an acceptance band. The digital filter may be placed within a stereo AM receiver to monitor the pilot tone of the incoming signal with clocking pulses provided by the IF stage of the radio receiver.

Abstract: A multiprocessing three level memory hierarchy implementation is described which uses a "write" flag and a "share" flag per page of information stored in a level three main memory. These two flag bits are utilized to communicate from main memory at level three to private and shared caches at memory levels one and two how a given page of information is to be used. Essentially, pages which can be both written and shared are moved from main memory to the shared level two cache and then to the shared level one cache, with the processors executing from the shared level one cache. All other pages are moved from main memory to the private level two and level one caches of the requesting processor. Thus, a processor executes either from its private or shared level one cache. This allows several processors to share a level three common main memory without encountering cross interrogation overhead.

Abstract: A data processing apparatus is provided with a keyboard and a programmable read-only memory, for example of EPROM type, for durably preserving data which define the manner of operation of the apparatus. A programming circuit connected to the apparatus allows a new memory of the same type to be programmed either by automatic recording of data contained in the original EPROM memory, or by data entered by means of the keyboard in order to make available a new read-only memory provided with data modified relative to the data of the original memory.

Abstract: A dual fetch microsequencer having two single-ported microprogram memories wherein both the sequential and jump address microinstructions of a binary conditional branch can be simultaneously prefetched, one from each memory. The microprogram is assembled so that the sequential and jump addresses of each branch have opposite odd/even polarities. Accordingly, with all odd addresses in one memory and even in the other, the first instruction of both possible paths can always be prefetched simultaneously. When a conditional branch microinstruction is loaded into the execution register, its jump address or a value corresponding to it is transferred to the address register for the appropriate microprogram memory. The address of the microinstruction in the execution register is incremented and transferred to the address register of the other microprogram memory. Prefetch delays are thereby reduced.

Abstract: The present invention provides a bus protocol interface circuit for the peripheral units that prevents a conflict in bus requests between the peripheral units and permits bipolar drivers to be used for fast operation. The interface circuit comprises a logic means coupled to the bus acknowledgment line input terminal and the bus acknowledgment line output terminal for generating a logic output signal responsive to the signals on the bus acknowledgement line input and output terminals, and latching means coupled between the bus request line and the bus request line terminal, and further connected to the output of the logic means and the bus acknowledgment line output terminal, for latching into a state consistent with a bus request signal from any one of the peripheral units and for unlatching from the consistent state upon receipt of a bus acknowledgment signal in response to the bus request signal.