Abstract: A peripheral device subsystem enables its peripheral devices to operate asynchronously with respect to attaches hosts through the use of managed buffers, new multiple data transfer modes, control and error recovery operations. In a preferred first or buffer mode of operation, all data of each record being transferred can be resident in a buffer before transfer to either a host or device. For a host to device write transfer, receipt of such a record by the buffer results in the subsystem signaling to the host a completion of a transfer to an addressed device even though the device has received none or only part of the data. In a second or tape write mode, recording data in a peripheral device, such as a tape recorder, completion of recording is not signaled until after the buffer has transferred the data to the recorder.

Abstract: The present invention discloses a data processing system where a plurality of vector registers consisting of plurality of elements are provided between a main memory unit and an operational processing unit, the desired data is transferred to the vector registers from the main memory unit and is held therein, and various processings such as a logical operation are carried out by sequentially accessing the elements within said vector registers. The present invention also includes a plurality of memory banks which can be independently accessed and are provided for the vector registers. A series of elements of each vector register are interleaved in the plurality of memory banks and the elements having the same numbering in each vector register are arranged in the same memory bank. Timing necessary for starting access to a series of elements of said vector registers are specified for each class of processing, so that the vector operation processings can be done very effectively and without operand collision.

Abstract: A program for determining the data for translation and key PROMs in a mapping system maps an A group of input states into an AK X AT A map and a B group of input states into a BK X BT B map. The smaller B group is mapped first with even packing in which the number of mapped elements assigned each BT state is maintained approximately equal as mapped elements are assigned BT locations. The larger A group is mapped last with close packing in which mapped elements are assigned preferentially to the AT state with the most previously mapped elements. The A group and B group are each ordered according to the number of mapped elements associated therewith from most to least and mapped in sequential order if possible.

Abstract: There are sequencers and format registers which create variable length digital data signal fields and associated field attributes, both with the fields and operations performed on the fields in a random access memory with a central processing unit having comprehensive processing capability, including arithmetic, field and record looping, compare, move and jump, look-up and disk read/write functions, I/O keyboard, display, print types of processing. The sequencers and associated format registers allow and manage comprehensive association of attributes with variable length digital data signal fields.

Abstract: A memory subsystem which couples to a multiword bus for processing memory requests received therefrom includes at least a pair of independently addressable dynamic memory module units. Each memory unit includes a number of rows of random access memory (RAM) chips. The subsystem further includes an adder circuit, a pair of tristate operated address register circuits and timing circuits. The address circuits include a pair of tristate operated address registers which couple to the bus and to the set of address lines to each memory unit. In response to a memory request, the registers store row and column address portions of a chip address of the memory request. A multibit adder circuit which couples to the bus is connected to increment by one the low order column address portion when the least significant address bit of the memory request indicates a subboundary address condition thereby enabling access to a pair of sequential word locations.

Abstract: A dual-processor, general purpose mini-computer which is programmed as a front-end data communications processor and is called a Network Support Processor. Data transfer commands received from a main host computer are executed and result messages are returned to the main host computer by the Network Support Processor. A base connection module providing slide-in connector cards houses and supports circuit cards which make up the Network Support Processor. These cards include a master controller which includes a master processor card, a master memory control card and an Interface Card which connects to a main host computer and to one or more line communications processors, each of which may handle up to 16 data communications lines. A slave controller likewise includes a slave processor circuit card, and a slave memory control circuit card. A series of slide-in memory cards forming a shared memory storage means connect to both the master and the slave memory control circuit cards.

Abstract: A microprocessor controlled data analyzing system is provided for use with a clinical spectrophotometer, such as the Abbott Bichromatic Analyzer (ABA-100), which is used for testing samples of serum derived from patients' blood. The data analyzing system of the invention serves to analyze the outputs from the spectrophotometer, and to transform the outputs into reportable units. The data analyzing system is capable of providing the operator with full instructions as to any particular test and to control the spectrophotometer to perform such a test.

Abstract: Base connection modules are used to house slide-in cards which form a Network Support Processor which executes data transfer operations for up to four main host computers. One Network Support Processor can control up to four Line Support Processors, each one of which manages up to 16 Line Adapters connected, via data communication lines, to remote terminals. The line Support Processor, via its Line Adapters, handles a wide variety of communication line disciplines but provides a common discipline to its Network Support Processor and the host computer.

Abstract: In a data processing and distribution system, a data sorter is disclosed for receiving formatted blocks of digital data, acting on those blocks according to the informational content stored therein and responsive to control data stored within the data sorter, and generating sorting tags to be added to the data blocks for proper identification by one or more data processors. Selected portions of each data block provide addressing signals to a memory which output data is compared to specified values. For one value of memory output data, the entire data block is dumped; for a second value, the contents of the addressed memory location are changed to a selected value; for a small range of values of memory output data, a new memory location is accessed; and for the balance of the values, the memory output data is the sorting tag to be combined with the data block.

Abstract: A method and apparatus for numerically controlling a machine tool having at least two tools which are arranged to move in unison with a constant position relationship with respect to one another, the tools being moved relative to a workpiece in accordance with absolute commands to machine a workpiece in a prescribed manner. A single current position register, comprising a section for storing X coordinates and a section for storing Z coordinates, is provided to store the current position of a first tool. Further provided are arithmetic means, responsive to a command for setting coordinates, for computing the current position of a second tool, as well as pulse distribution means.

Abstract: Various size frames or pages of information elements stored in a computer system can be simultaneously displayed on a screen-based terminal. The computer processor identifies the screen position the user selects for each of the stored pages and the top-to-bottom order of the pages with respect to visibility in the event that pages overlap. The processor selects the pages in descending order, topmost page first. Information elements of selected pages are transferred to appropriate locations in a display memory only in the event that an auxiliary memory registers that an information element has not priorly been transferred to those locations. After all the pages are transferred, background data is written into each display memory location that the auxiliary memory registers as not having an information element transferred thereto. The display memory is scanned in a conventional manner to apply the display information therein to the viewing screen.

Abstract: A peripheral device subsystem enables its peripheral devices to operate asynchronously with respect to attaches hosts through the use of managed buffers, new multiple data transfer modes, control and error recovery operations. In a preferred first or buffer mode of operation, all data of each record being transferred can be resident in a buffer before transfer to either a host or device. For a host to device write transfer, receipt of such a record by the buffer results in the subsystem signaling to the host a completion of a transfer to an addressed device even though the device has received none or only part of the data. In a second or tape write mode, recording data in a peripheral device, such as a tape recorder, completion of recording is not signaled until after the buffer has transferred the data to the recorder.

Abstract: A memory controller couples to a bus and controls a number of memory module units or memory modules. The controller includes a number of queue circuits for processing a variety of different types of memory requests received from a number of command generating units coupled to the bus requiring the controller to operate in a corresponding number of different modes. The controller includes queue start timing control apparatus which couples to the modules and to the queue circuits for resolving conflicts between the types of requests and the internal operations required to be performed by the controller within a minimum of time.

Abstract: A multiprocessor system comprising a plurality of processors and a memory unit which are connected through a common bus whereby each processor communicates with the memory through the bus. Communication among processors is effected by storing in a plurality of memory zones the messages intended for the several processors. The memory zones are each dedicated to one processors, but are accessible to all the processors. The communication among processors is performed by sending a notify signal on the common bus which is identified only by the processor for which it is intended. The notify signal is acknowledged by the notified processor without interrupting its ongoing operation. The notified processor subsequently accesses the memory unit and reads the message in the appropriate memory zone.

Abstract: Data processing workloads are balanced between a plurality of data processing units, such as control units of a peripheral system, based upon tallies of data processing delays. The workloads are arranged in work allocations, such as assignment of peripheral devices to a control unit; a separate delay tally is kept for each work allocation along with a summation of all delays in each control unit. When a tally threshold in any data processing unit is exceeded, load balance is examined. Upon a predetermined imbalance, a work allocation having a delay tally equal to a mean value of the different delay summations is transferred to a data processing unit having a lower delay summation.