Abstract: The operation of an electronic appliance, such as a cassette tape deck, is controlled completely or partially by switch operation. The appliance includes a memory for storage of control information, setting devices, such as switches, for entering the control information, a memory lock or latch for controlling the operating state of the appliance based on the control information supplied from the memory or from the setting devices to the memory lock, and for locking the appliance into such operating state, a display arrangement adapted for display of the setting information and for display of the information in the memory lock, and a setting change display indicator. The setting information stored in the memory can be checked by actuating a check switch, which causes the setting information stored in the memory to be displayed without affecting the operating state in which the appliance is locked.

Abstract: This disclosure relates to a network of reduction processors for the evaluation of one or more functions which are stored in memory in the form of a series of nodes of a treelike graph where the nodes implement a variable-free applicative language. The respective function operators are reduced through a progressive series of transformations or substitutions until a result is obtained. During the reduction process, the processor transfers nodes to and from memory and performs various operations as required on those nodes. The processor can also create new nodes in memory and delete unused ones.

Abstract: A digital computer system having a memory for storing and providing data including instructions and a processor for processing data in response to the instructions and providing memory operation specifiers to the memory which specify an address of a data item and the memory operation to be performed on it. The instructions in the digital computer system include operation codes belonging to more than one set of operation codes and names representing items to be processed in the operation specified by the operation code. The data in memory further includes name table entries. Each name table entry corresponds to a name and contains information specifying the address of the item represented by the name. The processor includes apparatus for decoding each operation code in response to the operation code and to a dialect value contained in the decoding apparatus which specifies which operation code set the operation code being decoded belongs to.

Abstract: Analog servo-positioning signals transduced from a recorded member, such as embedded servo signals recorded on a disc memory or the like, which are to be compared to one another in order to derive an error signal indicative of off-track position deviations, are normalized for accurate responsive positioning changes by use of an analog-to-digital converter referenced by both a positive and a negative summation of the two analog signals and supplied with the individual analog signals as inputs, such that the digitalized output comprises a pair of digital signals, the first representative of the quotient of the first analog signal divided by the summation of the two analog signals, and the second representative of the second analog signal divided by the same summation of analog signals.

Abstract: A Segregator Functional Plane capable of dynamically segregating any number, or subset, of a Modular Array Processor's functional planes, either in terms of control or data exchange, or both, from the remainder. This is provided by interspersing a number of Segregator Functional Planes throughout the Array Processor so that a Segregator Functional Plane is architecturally located between each of the adjacent subsets of the Array Processor's functional planes. The Segregator Functional Plane nominally includes an array of pseudomodules that corresponds to the module arrays of the other functional planes of the Array Processor so that a pseudo-module is architecturally present between correspondingly adjacent modules of each Elemental Processor. These pseudo-modules are comprised of switches that may be commonly activated to functionally sever their respective Elemental Processor data bus lines.

Abstract: An electronic controller having a detachably mounted front panel unit on which display devices and control elements are arranged is disclosed. By means of the control elements, the process variables and the control parameters are changed incrementally. Values of the control parameter, process variables, and the selected control parameter are indicated by the display devices. To provide a compact, independent front panel unit which can be removed from the main housing of the controller for protection against unauthorized operation, the front panel unit is provided with a slave microprocessor which is connected via a plug-in connector to a master microprocessor in the main housing. Because the master microprocessor operates independently of the front panel mounted slave microprocessor, the front panel unit can be removed without affecting the operation of the controller.

Abstract: An address matcher and process for same used as an aid in debugging computer programs. Each of a plurality of random access memories (RAMs) is addressed by a different subfield of a computer memory address so that each access of the computer memory also causes a read of each of the RAMs. Each RAM is programmed with encoded data to define upper and lower block addresses for that subfield of the computer memory address with which it is associated. An output circuit decodes the encoded data read from each of the RAMs as a result of a computer memory access and generates a signal if the computer memory address lies within the monitored address block.

Abstract: A cache memory for a data processing system having a tag array in which each tag word represents a predetermined plurality or block group of consecutively addressable data block locations in a data array. The lower order set address bits concurrently access the tag word and its associated group of block locations in the data array while individual blocks within the group are accessed by supplemental block bits. Each tag word read out must compare equal with the high order bits of the address and an accompanying validity bit for each block location in its group must be set in order to effect a hit. Also described are circuits for writing into the cache and adapting the cache to a multi-cache arrangement.

Abstract: An automated interactive game, instruction and reference system having an optical laser videodisc player unit and using a videodisc record on which are recorded segmented groups of graphic and pictorial video information data interspersed with segmented groups of system control and programming data, a television video display unit, a user command/response unit having user manual input controls of variable functions and variable labelling means therefor to indicate the current function as established by signals from said videodisc record, and control processor means for receiving short segments of programming data from said videodisc record and distributing information signals from said videodisc record to the other units in accordance with said programming data.

Abstract: With this circuit arrangement a plurality of control commands can be inputted into a microcomputer system by means of only a single input channel and the microprocessor is relieved of the operation of scanning the peripherals for detecting the presence of control commands. By means of a release or enabling signal the microprocessor signals its preparedness for receiving interruptions, and the release or enabling signal activates a scanning and comparator unit arranged between an interrupt requirement input of the microprocessor and a peripheral unit. Thereafter the scanning and comparator unit scans control command transmitters grouped together in the peripheral unit and characterized by an address and compares the switching state thereof with a switching state which is stored under the same address. If the two switching states are different, there is generated an interrupt requirement or requisition and the stored switching state is adapted to the switching state of the control command transmitter.

Abstract: A microcomputer used in the multi-function watch comprises, in addition to its conventional circuits such as the program memory 1, the data memory 7 and the arithmetic and logic unit 6, a counter 13 with a counting capacity of 100. The counter can be set in operation and stopped by instructions forming part of a manually triggered program of the microcomputer. When it is operating, it counts pulses M1 of a frequency of 100 Hz which are supplied by the time base 10, 11 of the watch. When it reaches its maximum capacity, it is reset to zero and produces a chronographic time base signal T which sets the microcomputer in operation. This microcomputer then carries out a program which processes and causes display of the data relating to seconds, minutes and hours of chronographic time, which are stored in the data memory 7.

Abstract: A number of intelligent bus interface units (100) are provided in a matrix of orthogonal lines interconnecting processor modules (110) and memory control unit (MCU) modules (112). The matrix is composed of processor buses (105) and corresponding control lines; and memory buses (107) with corresponding control lines (108). At the intersection of these lines is a bus interface unit node (100). The bus interface units function to pass memory requests from a processor module to a memory module attached to an MCU node and to pass any data associated with the requests. The memory bus is a packet-oriented bus. Accesses are handled by means of a series of messages transmitted by message generator (417) in accordance with a specific control protocol. Packets comprising one or more bus transmission slots are issued sequentially and contiguously. Each slot in a packet includes an opcode, address, data, control, and parity-check bits. Write-request packets and read-request packets are issued to the memory-control unit.

Abstract: A memory management unit of use in a memory management system. The memory management unit selectively maps a logical address to a respective physical address in accordance with a selected one of a plurality of segment descriptors, each of which defines a logical-to-physical address mapping and a range of address spaces for which such mapping is valid. The mapping is achieved using an improved associative memory circuit. Means are provided to detect mapping conflicts between new segment descriptors and segment descriptors already stored, and to prevent the storage of such conflicting segment descriptors. A method and circuit are provided to coordinate the parallel operation of a plurality of the memory management units or the like.

Abstract: A data processing system using separate fixed point and floating point computation units and a single control store means for controlling the operations of both units, the units being responsive to commonly shared control fields of the microinstructions supplied from the control store means during their respective operations.

Abstract: A digital data bus system operating asynchronously with a fixed clock and having a automatically variable data rate selected by sending and receiving units. A master clock is generated by a master controller and distributed to one or more peripheral controllers of the data bus system through a single clock line. In addition to address/data lines, a single handshake hold signal is shared by the master and all peripheral controllers. All data transfers are executed on a bus clock pulse and data transfer rate is controlled by the sending and receiving units through operation of the hold signal. A receiving unit not ready to receive information on the bus will assert hold signal on hold signal line and the transmitting unit will maintain the information presently on the bus during each clock period in of which hold signal is asserted. Data transfer is executed on next clock pulse after termination of hold signal.

Abstract: A data transfer system comprises data retaining means for retaining n-bit digital data (n being an integer), serial/parallel data converting means for converting the n-bit digital data transferred from the data retaining means from parallel data to serial data or vice versa in synchronism with first clock signals generated at a first clock frequency, counting means for counting second clock signals generated at a second clock frequency, and control means for transferring the n-bit digital data from the data retaining means to the serial/parallel data converting means each time the counting means counts a predetermined number of clock signals.

Abstract: A central sub-system of a data processing system, including an operator console controlling a service processor, is divided into several sub-units, functioning separately from each other. The sub-units include processors that are connected together and to a common controller for a common memory unit by data, address and control buses. Each sub-unit includes a configuration device that stores an appurtenance indicator derived from the service processor in response to sub-unit initialization, and enables its associated sub-unit to exchange data with the memory unit. The sub-unit having the highest priority of the sub-units attempting to access the memory units is connected to the memory unit by the controller. A single configuration memory stores an indication of the sub-units in service in the central sub-system. The configuration memory is addressed each time the memory unit is addressed by a signal indicative of the appurtenance indicator derived from the selected sub-unit.

Abstract: A data-transfer controlling system comprising a bus-control unit connected to a common bus for controlling data transfer through the bus and a plurality of transmitter/receiver units for transferring data through the common bus to each other. The bus is comprised of a transfer-request signal line connected to each of the transmitter/receiver units, one or two permission-signal lines, for permitting transfer of data by a transmitter/receiver unit which has been generating a transfer-request signal, an acknowledge signal line, and a transfer-end signal line. The bus does not include a busy-interlock signal line, which was included in the prior art. The transmitter/receiver unit which has received the permission signal begins to transfer data when both of the permission signal and the transfer-end signal are terminated.

Abstract: A vital communication system includes a conventional, that is non-vital, communication link, a transmitter and a receiver. The transmitter is responsive to input data, and provides for encoding and transmission as well as checking of its own input arrangement. The encoding and transmission is effected by a program driven device, but as loaded the program is incomplete. The checking produces certain check words which are used to complete the program so that only in those instances in which the checks are passed, will an appropriate message be transmitted. The receiver includes a decoder logic as well as a decoder check logic. The messages are decoded and applied to an output device. The decoder check logic checks that the information supplied to the output device corresponds to the decoded information, and if the check is passed, the output device is enabled to output the information to the outside world.

Abstract: A programmable logic array (PLA) is comprised of double-personalized cells conventionally arranged in an AND and OR array. In order to activate redundant or Don't Care positions, i.e., array positions not being used for performing the respective PLA functions, control circuits are provided preceding the AND array as well as between the AND and the OR array. This allows an increase in the number of possible PLA functions to be performed by a given PLA thus providing PLA's with improved functional density. The control circuits essentially consist of two-stage AND-OR circuits being fully compatible with the AND and OR array technology of the PLA. For optimum utilization of the Don't Care positions and planes, each functional input can be switched to any discretionary functional line of the PLA. By providing an additional control line in the OR array, the control logic for the entire OR array is reduced to only two AND gates.