Abstract: A semiconductor device is provided. The semiconductor device includes a first transistor on a first side of a shallow trench isolation (STI) region and a second transistor on a second side of the STI region. The first transistor includes a first conductive portion having a second conductivity type formed within a well having a first conductivity type, a first nanowire connected to the first conductive portion and a first active area, and a first gate surrounding the first nanowire. The second transistor includes a second conductive portion having the second conductivity type formed within the well, a second nanowire connected to the second conductive portion and a second active area, and a second gate surrounding the second nanowire. Excess current from an ESD event travels through the first conductive portion through the well to the second conductive portion bypassing the first nanowire and the second nanowire.

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes selectively depositing a metal layer overlying a metal line of a metallization layer that is disposed in an ILD layer of dielectric material while an upper surface of the ILD layer that is laterally adjacent to the metal line is exposed. A hard mask layer is formed overlying the upper surface of the ILD layer laterally adjacent to the metal layer. The metal layer is removed to expose the metal line while leaving the hard mask layer intact. An interconnect is formed with the metal line adjacent to the hard mask layer.

Abstract: A change in electrical characteristics of a semiconductor device including an interlayer insulating film over a transistor including an oxide semiconductor as a semiconductor film is suppressed. The structure includes a first insulating film which includes a void portion in a step region formed by a source electrode and a drain electrode over the semiconductor film and contains silicon oxide as a component, and a second insulating film containing silicon nitride, which is provided in contact with the first insulating film to cover the void portion in the first insulating film. The structure can prevent the void portion generated in the first insulating film from expanding outward.

Abstract: An ionizer includes a body extending in a first direction, a sheath gas nozzle installed in a lower portion of the body and having a spray hole and an electrode needle disposed within the spray hole to generate a corona discharge, a gas supply provided in the body and configured to be in fluid communication with the spray hole to supply a gas to the spray hole such that ions generated by the electrode needle are spayed out to the outside of the ionizer from the spray hole, and a pair of first and second guiding plates disposed at opposite sides of the sheath gas nozzle and extending downward from first and second sides of the body opposite to each other to guide the ions sprayed from the spray hole to be directed to a target. A semiconductor device may be manufactured using the ionizer.

Abstract: A vertical junction field effect transistor (JFET) is supported by a semiconductor substrate that includes a source region within the semiconductor substrate doped with a first conductivity-type dopant. A fin of semiconductor material doped with the first conductivity-type dopant has a first end in contact with the source region and further includes a second end and sidewalls between the first and second ends. A drain region is formed of first epitaxial material grown from the second end of the fin and doped with the first conductivity-type dopant. A gate structure is formed of second epitaxial material grown from the sidewalls of the fin and doped with a second conductivity-type dopant.

Abstract: There is provided a silicon carbide semiconductor device allowing for increased switching speed with a simpler configuration. A silicon carbide semiconductor device includes: a gate electrode provided on a gate insulating film; and a gate pad. The gate electrode includes a first comb-tooth shaped electrode portion extending from outside of the gate pad toward a circumferential edge portion of the gate pad and overlapping with the gate pad at the circumferential edge portion of the gate pad when viewed in a plan view. A p+ region includes: a central portion overlapping with the gate pad when viewed in the plan view; and a peripheral portion extending from the central portion toward the outside of the gate pad, the peripheral portion being provided to face the first comb-tooth shaped electrode portion of the gate electrode with a space interposed therebetween.

Abstract: A display panel is provided. A display panel includes a plurality of pixels and a plurality of gate lines. The pixels include a first pixel, a second pixel and a third pixel. The gate lines include a first gate line, a second gate line and a third gate line. The first gate line drives the first pixel. The second gate line drives the second pixel. The third gate line drives the third pixel. The first gate line, the second gate line and the third gate line are disposed sequentially and driven at different time. The first pixel and the second pixel are arranged respectively at two opposite sides of the first gate line and the second gate line. The second pixel and the third pixel are arrange between the second gate line and the third gate line.

Abstract: A semiconductor device includes a first semiconductor layer including a recess region and protrusions defined by the recessed region, first insulating patterns provided on the protrusions and extending to sidewalls of the protrusions, and a second semiconductor layer to fill the recess region and cover the first insulating patterns. The protrusions includes a first group of protrusions spaced apart from each other in a first direction to constitute a row and a second group of protrusions spaced from the first group of protrusions in a second direction intersecting the first direction and spaced from each other in the first direction to constitute a row. The second group of protrusions are shifted from the first group of protrusions in the first direction.

Abstract: Disclosed are an npn-type bipolar transistor as a nitride semiconductor device having good characteristics, and a method of manufacturing the same. A so-called pn epitaxial substrate has a structure wherein an n-type collector layer and a p-type base layer of a three-layer structure are provided over a substrate. The three-layer structure includes first (lower layer side), second, and third (upper layer side) p-type base layers which differ in thickness and p-type impurity concentration. In a partial region inside the second p-type base layer located as an intermediate layer in the p-type base layer of the three-layer structure, an n-type emitter region is formed by ion implantation.

Abstract: A light emitting device includes: a base member; and a plurality of light emitting elements mounted on the base member. The plurality of light emitting elements includes: at least one first light emitting element having a side surface uncovered by a light reflective member; and at least one second light emitting element having a side surface covered by the light reflective member.

Abstract: Provided is a nano-structured light-emitting device including: a first type semiconductor layer; a plurality of nanostructures which are formed on the first type semiconductor layer and include nanocores, and active layers and second type semiconductor layers that enclose surfaces of the nanocores; an electrode layer which encloses and covers the plurality of nanostructures; and a plurality of resistant layers which are formed on the electrode layer and respectively correspond to the plurality of nanostructures.

Abstract: A semiconductor device includes a substrate having a first region and a second region, an n-type transistor in the first region, the n-type transistor comprising a first set of source/drain features, and a p-type transistor in the second region, the p-type transistor comprising a second set of source/drain features. The second set of source/drain features extend deeper than the first set of source/drain features.

Abstract: Described herein are techniques related a precision deposition of unpackaged semiconductor devices (“dies”) onto a substrate. This Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: An array substrate and manufacturing thereof are provided. The array substrate comprises gate lines, first data lines, second data lines and N×M pixel units defined by the gate lines intersecting with the first data lines and the second data lines. A repairing line for each column of the pixel units is provided for a region at which at least one row of pixel units are located. Projections of two ends of the repairing line on the substrate respectively overlap with regions at which the first data line and the second data line of the same column of pixel units are located, and the repairing line is isolated from the first data line and the second data line.

Abstract: A method for manufacturing a semiconductor device includes: preparing a semiconductor substrate, in which a first semiconductor layer is formed on a substrate; forming a first concave portion in the first semiconductor layer; forming trenches on the first semiconductor layer in the first concave portion; epitaxially growing a second semiconductor layer for embedding in each trench and the first concave portion; forming a SJ structure having PN columns including the second semiconductor layer in each trench and the first semiconductor layer between the trenches; and forming the vertical MOSFET by: forming a channel layer and a source region contacting the channel layer on the SJ structure; forming a gate electrode over the channel layer through a gate insulating film; forming a source electrode connected to the source region; and forming a drain electrode on a rear of the substrate.

Abstract: This invention provides a semiconductor package, including a substrate, a plurality of semiconductor elements disposed on the substrate, at least one shielding member disposed between at least two of the semiconductor elements, and an encapsulant encapsulating the semiconductor elements and shielding members. Through the shielding member, electromagnetic interference caused among semiconductor elements can be prevented.

Abstract: A nanostructure semiconductor light-emitting device includes a base layer formed of a first conductivity-type semiconductor, a first material layer disposed on the base layer and including a plurality of openings, a plurality of light-emitting nanostructures, each of which extends through each of the plurality of openings and includes a nanocore formed of a first conductivity-type semiconductor, an active layer and a second conductivity-type semiconductor shell layer, sequentially disposed on the nanocore, a filling layer disposed on the first material layer, wherein the filling layer fills spaces between the plurality of light-emitting nanostructures and a portion of each of the plurality of light-emitting nanostructures is exposed by the filling layer, a second conductivity-type semiconductor extension layer disposed on the filling layer and covering the exposed portion of each of the plurality of light-emitting nanostructures, and a contact electrode layer disposed on the second conductivity-type semicondu

Abstract: Embodiments of the disclosure provide methods and system for correcting lithographic film stress/strain variations on a semiconductor substrate using laser energy treatment process. In one embodiment, a method for correcting film stress/strain variations on a substrate includes performing a measurement process in a metrology tool on a substrate to obtain a substrate distortion or an overlay error map, determining dose of laser energy in a computing system to correct film stress/strain variations or substrate distortion based on the overlay error map, and providing a laser energy treatment recipe to a laser energy apparatus based on the dose of laser energy determined to correct substrate distortion or film stress/strain variations.

Abstract: A package on package semiconductor structure includes a first package positioned above a first surface of a substrate, a second package positioned above the first package, and a first thermal element positioned between the first package and the second package, wherein the first thermal element is separated from the second package by an air gap and the thermal element provides a heat path for heat generated by the first package.

Abstract: An embedded flash memory device is provided. A gate stack includes a control gate arranged over a floating gate. An erase gate is arranged adjacent to a first side of the gate stack. A word line is arranged adjacent to a second side of the gate stack that is opposite the first side. The word line includes a word line ledge exhibiting a reduced height relative to a top surface of the word line and on an opposite side of the word line as the gate stack. A polysilicon logic gate has a top surface approximately even with the word line ledge. An ILD layer is arranged over the gate stack, the erase gate, the polysilicon logic gate, and the word lines. A contact extends through the ILD layer. A method of manufacturing the embedded flash memory device is also provided.