Abstract: Electrical fuse (eFuse) and resistor structures and methods of manufacture are provided. The method includes forming metal gates having a capping material on a top surface thereof. The method further includes protecting the metal gates and the capping material during an etching process which forms a recess in a dielectric material. The method further includes forming an insulator material and metal material within the recess. The method further includes forming a contact in direct electrical contact with the metal material.

Abstract: A method for fabricating a semiconductor device includes the following steps: providing a substrate having an epitaxial layer, a gate structure and an interlayer dielectric thereon, where the epitaxial structure is disposed at sides of the gate structure and the interlayer dielectric covering the epitaxial structure; forming an opening in the interlayer dielectric so that the surface of the epitaxial layer is exposed from the bottom of the opening; performing a rapid thermal process in an inert environment until non-conductive material is generated on the surface of the epitaxial layer; and removing the non-conductive material.

Abstract: A die package having a plurality of connection pads, a plurality of wire leads having metal cores with a defined core diameter, and a dielectric layer surrounding the metal cores having a defined dielectric thickness, at least one first connection pad held in a mold compound covering the die and the plurality of leads connected to at least one metal core, and at least one second connection pad held in the mold compound covering the die and the plurality of leads connected to at least one metal core. Further, the present invention relates to a method for manufacturing a substrate less die package.

Abstract: A display device and a method for manufacturing the same are provided. The display device includes a first substrate, a second substrate and a light curable sealant. The first substrate has a displaying area and a non-displaying area, in which the displaying area includes a pixel array, and the non-displaying area includes a driving circuit. The driving circuit includes at least a capacitor which is made of transparent conductive material. The second substrate has an opaque area. The light curable sealant is located between the first substrate and the second substrate. When viewing from a normal vector of the first substrate or the second substrate, the light curable sealant, the capacitor and the opaque area are at least partially overlapped with each other.

Abstract: This wiring board is provided with: an insulating base that has a lateral surface having an incision part; an electrode that is provided on the inner surface of the incision part; and a wiring conductor that is provided within the insulating base or on the surface of the insulating base and is electrically connected to the electrode via a connection conductor. The width of the incision part is larger than the depth thereof, and the connection conductor is connected to the electrode at an end of the incision part in the width direction. An electronic device according to the present invention is provided with this wiring board and an electronic component that is mounted to the upper surface of this wiring board.

Abstract: The invention provides a semiconductor package. The semiconductor package includes a lead frame including a die paddle. A supporting bar connects to the die paddle, extending in an outward direction from the die paddle. At least two power leads are separated from the die paddle and the supporting bar, having first terminals close to the die paddle and second terminals extending outward from the die paddle. A power bar connects to the at least two power leads, having a supporting portion. A molding material encapsulates the lead frame leaving the supporting portion exposed.

Abstract: A light emitting device includes a package including a resin member having an inner side surface defining a recess, and a lead frame supported by the resin member and arranged at a bottom surface of the recess; and a light emitting element electrically connected to the lead frame. An outer side surface of the resin member at a portion corresponding to the recess is at least partially covered with a reflective film.

Abstract: Provided herein is an apparatus, including a substrate; an etch stop layer overlying the substrate, wherein the etch stop layer is substantially resistant to etching conditions; and a patterned layer overlying the etch stop layer, wherein the patterned layer is substantially labile to the etching conditions, and wherein the patterned layer comprises a number of features including substantially consistent feature profiles among regions of high feature density and regions of low feature density.

Abstract: The present invention provides a color filter substrate, a display device and a detection method thereof, aims to solve the problems of difficulty in failure positioning and low detection efficiency in existing display panels. The color filter substrate comprises a plurality of sub-pixels arranged in an array, each of the sub-pixels is provided with a color filter, and at least a part of columns of sub-pixels are marked column of sub-pixels. The shapes of the color filters of a part of sub-pixels of the marked column of sub-pixels are different from those of the remaining sub-pixels. The display device comprises the above-mentioned color filter substrate. The color filter substrate can be used in the display device, particularly suitable for the display device which adopts double side GOA circuits.

Abstract: An LED light source performance compensation apparatus and a white-light LED light-emitting device. The LED light source performance compensation apparatus comprises: a light transmissive supporting member (101), wherein the light transmissive supporting member (101) is provided with a light performance parameter regulation member (102); and after secondary light of which the wavelength is 380 nm-780 nm and which is emitted by an LED light source (103) passes through the performance compensation apparatus, light performance parameters are adjusted. The LED light source performance compensation apparatus can effectively regulate the light performance parameters of the LED light source, thereby remedying the defects of the secondary light emitted by an existing finished LED light source in terms of light performance parameters.

Abstract: An electronic support structure comprising one or more layers of copper features such as copper routing layers, laminated within a dielectric material comprising continuous glass fibers in a polymer matrix wherein pairs of adjacent layers of copper features are coupled by a via layer, and where terminations on at least one side of the electronic support structure comprise a modified bond-on-trace attachment sites comprising selectively exposed top and partial side surfaces of copper features in an outer layer of copper features for conductive coupling solder.

Abstract: This wiring board is provided with: an insulating base that has a lateral surface having an incision part; an electrode that is provided on the inner surface of the incision part; and a wiring conductor that is provided within the insulating base or on the surface of the insulating base and is electrically connected to the electrode via a connection conductor. The width of the incision part is larger than the depth thereof, and the connection conductor is connected to the electrode at an end of the incision part in the width direction. An electronic device according to the present invention is provided with this wiring board and an electronic component that is mounted to the upper surface of this wiring board.

Abstract: The present invention relates to a substrate having an upper surface that is not parallel to a reference plane, wherein the substrate may include the upper surface or an upper layer which is inclined or inflexed. In addition, the present invention relates to a light emitting diode comprising an active layer that is not parallel to a reference plane. The light emitting diode of the present invention may be characterized in that the active layer is inflexed. Furthermore, the light emitting diode of the present invention may be characterized in that the side wall of the light emitting diode is inflexed. Moreover, the light emitting diode of the present invention may be characterized in that the side wall of the light emitting diode is inflexed and inclined. Through the configuration, the size of a chip is identically maintained, and the area of the active layer for emitting light is increased.

Abstract: A method for fabricating a semiconductor device includes forming a relaxed semiconductor layer on a substrate, the substrate comprising an n-type region and a p-type region. The method further includes forming a tensile strained semiconductor layer on the relaxed semiconductor layer, etching a portion of the tensile strained semiconductor layer in the p-type region, forming a compressive strained semiconductor layer on the tensile strained semiconductor layer in the p-type region, forming a first gate in the n-type region and a second gate in the p-type region, and forming a first set of source/drain features adjacent to the first gate and a second set of source/drain features adjacent to the second gate. The second set of source/drain features are deeper than the first set of source/drain features.

Abstract: The invention provides an array substrate and a manufacturing method thereof, a display panel and a display device, the array substrate includes a base substrate, and a data line, a switching device and a voltage compensation module arranged on the base substrate, the switching device is connected between the data line and the voltage compensation module so that the data line is electrically connected to the voltage compensation module when a voltage on the data line is lower than a preset low voltage or higher than a preset high voltage. The array substrate uses a PN junction as the switching device between the data line and the voltage compensation module, and due to a low leakage current between a P terminal and an N terminal of the PN junction, the power consumption of the array substrate can be reduced.

Abstract: A chemical mechanical planarization for a Group III arsenide material is provided in which at least one opening is formed within a dielectric layer located on a substrate. A Group III arsenide material is epitaxially grown within the at least one opening of the dielectric layer which extends above a topmost surface of the dielectric layer. The Group III arsenide material is planarized using at least one slurry composition to form coplanar surfaces of the Group III arsenide material and the dielectric layer, where a slurry composition of the at least one slurry composition polishes the Group III arsenide material selective to the topmost surface of the dielectric layer, and includes an abrasive, at least one pH modulator and an oxidizer, the at least one pH modulator including an acidic pH modulator, but lacks a basic pH modulator, and where the oxidizer suppresses generation of an arsine gas.

Abstract: A circuit including a semiconductor device having a set of space-charge control electrodes is provided. The set of space-charge control electrodes is located between a first terminal, such as a gate or a cathode, and a second terminal, such as a drain or an anode, of the device. The circuit includes a biasing network, which supplies an individual bias voltage to each of the set of space-charge control electrodes. The bias voltage for each space-charge control electrode can be: selected based on the bias voltages of each of the terminals and a location of the space-charge control electrode relative to the terminals and/or configured to deplete a region of the channel under the corresponding space-charge control electrode at an operating voltage applied to the second terminal.

Abstract: An organic light emitting diode (OLED) display includes a substrate in which an emission area and a non-emission area are defined, an OLED disposed in the emission area. The OLED display further includes a thin film transistor disposed in the non-emission area, a first insulation layer overlapping the thin film transistor in the non-emission area, a first storage capacitance electrode disposed in the emission area on the first insulation layer, a second insulation layer disposed to cover the first storage capacitance electrode and the thin film transistor except a portion of the thin film transistor, said portion of the thin film transistor being exposed through the second insulation later. The OLED display further includes an organic protective layer disposed on the second insulation layer, and an anode electrode of the OLED disposed on the second insulation layer, the anode electrode electrically connected to the thin film transistor.

Abstract: Method for chemical mechanical planarization is provided, which includes: forming a dielectric layer containing at least one opening, the dielectric layer is located on a substrate; epitaxially growing a germanium material within the at least one opening of the dielectric layer, the germanium material extending above a topmost surface of the dielectric layer; and planarizing the germanium material using at least one slurry composition to form coplanar surfaces of the germanium material and the dielectric layer, where a slurry composition of at least one slurry composition polishes the germanium material selective to the topmost surface of the dielectric layer, and includes an abrasive, at least one pH modulator, and an oxidizer, the at least one pH modulator including an acidic pH modulator, and lacking a basic pH modulator.

Abstract: A semiconductor device manufacturing method includes forming a silicon layer by epitaxial growth over a semiconductor substrate having a first area and a second area; forming a first gate oxide film by oxidizing the silicon layer; removing the first gate oxide film from the second area, while maintaining the first gate oxide film in the first area; thereafter, increasing a thickness of the first gate oxide film in the first area and simultaneously forming a second gate oxide film by oxidizing the silicon layer in the second area; and forming a first gate electrode and a second gate electrode over the first gate oxide film and the second gate oxide film, respectively, wherein after the formation of the first and second gate electrodes, the silicon layer in the first area is thicker than the silicon layer in the second area.