Patents Examined by Jami M Valentine
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Patent number: 9780018Abstract: A power semiconductor package is disclosed. The power semiconductor package includes a leadframe having partially etched segments and at least one non-etched segment, a first semiconductor die having a first power transistor and a driver integrated circuit (IC) monolithically formed thereon, a second semiconductor die having a second power transistor, wherein the first semiconductor die and the second semiconductor die are configured for attachment to the partially etched segments, and wherein the partially etched segments and the at least one non-etched segment enable the first semiconductor die to be coupled to the second semiconductor die by a legless conductive clip.Type: GrantFiled: October 23, 2015Date of Patent: October 3, 2017Assignee: Infineon Technologies Americas Corp.Inventor: Eung San Cho
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Patent number: 9773797Abstract: According to one embodiment, a non-volatile memory device includes electrodes, an interlayer insulating film, at least one semiconductor layer, conductive layers, first and second insulating films. The electrodes are arranged in a first direction. The interlayer insulating film is provided between the electrodes. The semiconductor layer extends in the first direction in the electrodes and the interlayer insulating film. The conductive layers are provided between each of the electrodes and the semiconductor layer, and separated from each other in the first direction. The first insulating film is provided between the conductive layers and the semiconductor layer. The second insulating film is provided between each of the electrodes and the conductive layers, and extends between each of the electrodes and the interlayer insulating film adjacent to the each of the electrodes. A width of the conductive layers in the first direction is narrower than that of the second insulating film.Type: GrantFiled: January 24, 2017Date of Patent: September 26, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventor: Hiroki Yamashita
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Patent number: 9767962Abstract: Some embodiments include a capacitive chip having a plurality of capacitive units. The individual capacitive units include alternating electrode layers and dielectric layers in a capacitor stack. The capacitor stack extends across an undulating topography. The undulating topography has peaks and valleys with the peaks being elevationally offset relative to the valleys by a distance within a range of from about 30 microns to about 100 microns. The capacitor stack includes at least about 10 total layers. Some embodiments include apparatuses and multi-chip modules having capacitor chips.Type: GrantFiled: January 22, 2016Date of Patent: September 19, 2017Assignee: Micron Technology, Inc.Inventor: Fred D. Fishburn
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Patent number: 9766510Abstract: The present invention provides a pixel unit and an array substrate. The pixel electrode includes four branch sections to divide the pixel zone into four display domains, helping improve the large angle color shifting problem of a display product and also simplifying the structure of the pixel electrode and making the manufacturing process simple, and facilitating the production of large-size wide-angle display products. The array substrate of the present invention is composed, in the horizontal direction, of multiple pixel units. The pixel units each include a pixel electrode that includes four branch sections to divide the pixel zone into four display domains, helping improve the large angle color shifting problem of a display product, and the pixel electrode has a simple structure to simplify the manufacturing process and facilitate the production of large-size wide-angle display products.Type: GrantFiled: December 21, 2015Date of Patent: September 19, 2017Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventor: Lin Meng
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Patent number: 9768306Abstract: An array substrate and a display device are provided. A gate insulating layer and a gate electrode are formed on a semiconductor layer in sequence, the gate insulating layer and the gate electrode are located in a middle position of the semiconductor layer and have a uniform shape and size. In a region on the semiconductor layer that is not covered by the gate insulating layer, there is further provided a metal diffusion layer. A barrier layer includes a portion covering the gate insulating layer and the gate electrode and a portion located around the semiconductor layer. A passivation layer covers the semiconductor layer, the gate insulating layer, the gate electrode and the barrier layer. Source and drain electrodes are connected to the metal diffusion layer respectively, and a pixel electrode contacts with the drain electrode.Type: GrantFiled: May 10, 2016Date of Patent: September 19, 2017Assignee: BOE TECHNOLOGY GROUP CO., LTD.Inventors: Tianming Dai, Qi Yao, Feng Zhang, Zhangfeng Cao
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Patent number: 9761692Abstract: A method for fabricating semiconductor device preferably forms a stop layer composed of amorphous silicon between a first BM layer and a second BBM layer of one of the gate structure during the fabrication of a device having multi-VT gate structures. By doing so, it would be desirable to use the stop layer as a protecting layer during the etching process of work function metal layers and the second BBM layer so that the first BBM layer could be protected from etchant such as SC1 and the overall thickness of the first BBM layer and the performance of the device could be maintained.Type: GrantFiled: May 23, 2016Date of Patent: September 12, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chao-Hung Lin, Shih-Hung Tsai, Jyh-Shyang Jenq
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Patent number: 9759961Abstract: The present invention discloses an array substrate, a display panel, and a display device, for solving a problem of tip discharge a comb pixel electrode comprised in a sub-pixel unit in the prior art, which produces discharge to surrounding data lines, gate lines, and neighboring pixel electrodes, so that neighboring sub-pixel units are subject to interference and display effect is influenced. The array substrate comprises a base plate, the base plate is further provided with a plurality of sub-pixel units, each of the sub-pixel units comprises a pixel electrode of a comb structure, and the base plate is further provided with a shielding electrode which is electrically connected with the pixel electrode.Type: GrantFiled: April 20, 2015Date of Patent: September 12, 2017Assignee: BOE TECHNOLOGY GROUP CO., LTD.Inventors: Pan Li, Wenbo Li, Yong Qiao, Hongfei Cheng, Jianbo Xian
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Patent number: 9754651Abstract: A magnetoresistive memory element is provided with a read module having a first pinned layer with a magnetoresistance that is readable by a read current received from an external circuit. A write module has a nanocontact that receives a write current from the external circuit and, in turn, imparts a spin torque to a free layer that functions as a shared storage layer for both the read module and the write module.Type: GrantFiled: April 25, 2016Date of Patent: September 5, 2017Assignee: Seagate Technology, LLCInventors: Oleg N. Mryasov, Thomas F. Ambrose, Werner Scholz
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Patent number: 9755192Abstract: A method of cutting a substrate includes: forming a first protective layer on a first surface of the substrate; forming a removal area where a portion of the first protective layer is removed by irradiating the first protective layer at the portion of the first protective layer with a first laser beam; and forming a cutting area by removing a portion of the substrate by irradiating the substrate with a second laser beam at the removal area, after irradiating the first protective layer with the first laser beam.Type: GrantFiled: December 11, 2015Date of Patent: September 5, 2017Assignee: Samsung Display Co., Ltd.Inventors: Junghwa You, Taeyong Kim, Hyojin Kim, Ilyoung Jeong, Gyoowan Han, Jekil Ryu, Jinho Lee
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Patent number: 9748391Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.Type: GrantFiled: February 24, 2017Date of Patent: August 29, 2017Assignee: Intel CorporationInventors: Robert S. Chau, Suman Datta, Jack Kavalieros, Justin K. Brask, Mark L. Doczy, Matthew Metz
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Patent number: 9741728Abstract: A method of manufacturing an embedded flash memory device is provided. A pair of gate stacks are formed spaced over a semiconductor substrate, and including floating gates and control gates over the floating gates. A common gate layer is formed over the gate stacks and the semiconductor substrate, and lining sidewalls of the gate stacks. A first etch is performed into the common gate layer to recess an upper surface of the common gate layer to below upper surfaces respectively of the gate stacks, and to form an erase gate between the gate stacks. Hard masks are respectively formed over the erase gate, a word line region of the common gate layer, and a logic gate region of the common gate layer. A second etch is performed into the common gate layer with the hard masks in place to concurrently form a word line and a logic gate.Type: GrantFiled: August 24, 2016Date of Patent: August 22, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Harry-Hak-Lay Chuang, Chang-Ming Wu, Shih-Chang Liu
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Patent number: 9735076Abstract: An epoxy resin composition for encapsulating a semiconductor device and a semiconductor device encapsulated by the epoxy resin composition, the composition including a base resin; a filler; a colorant; and a thermochromic pigment, wherein a color of the thermochromic pigment is irreversibly changed when a temperature thereof exceeds a predetermined temperature.Type: GrantFiled: May 24, 2016Date of Patent: August 15, 2017Assignee: SAMSUNG SDI CO., LTD.Inventors: Yoon Man Lee, So Yoon Kim
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Patent number: 9735203Abstract: Provided are 3D non-volatile memory devices and methods of fabricating the same. A 3D non-volatile memory device according to an embodiment of the present invention includes a plurality of conductive lines, which are separated from one another in parallel; a plurality of conductive planes, which extend across the plurality of conductive lines and are separated from one another in parallel; and non-volatile data storage layer patterns, which are respectively arranged at regions of intersection at which the plurality of conductive lines and the plurality of conductive planes cross each others.Type: GrantFiled: April 11, 2016Date of Patent: August 15, 2017Assignee: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATIONInventors: Cheol Seong Hwang, Jun Yeong Seok
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Patent number: 9735335Abstract: A thermoelectric conversion element includes a first electrode on provided a substrate; a pyroelectric film that is provided on the first electrode, is formed of a composite oxide having an ABO3-type perovskite structure, and generates a surface charge due to temperature change; and a second electrode provided on the pyroelectric film, in which the composite oxide which forms at least a portion of layer in the pyroelectric film contains at least Pb, Nb, and Ti, and is formed of tetragonal crystal which is oriented in the direction of {100} on the substrate.Type: GrantFiled: May 12, 2016Date of Patent: August 15, 2017Assignee: Seiko Epson CorporationInventors: Takayuki Yonemura, Toshiki Hara
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Patent number: 9728680Abstract: An optoelectronic device comprises microwires or nanowires, each of which comprises an alternation of passivated portions and of active portions, the active portions being surrounded with an active layer, where the active layers do not extend on the passivated portions.Type: GrantFiled: December 27, 2013Date of Patent: August 8, 2017Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES, ALEDIAInventors: Amélie Dussaigne, Alain Million, Anne-Laure Bavencove
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Patent number: 9721885Abstract: Electrical fuse (eFuse) and resistor structures and methods of manufacture are provided. The method includes forming metal gates having a capping material on a top surface thereof. The method further includes protecting the metal gates and the capping material during an etching process which forms a recess in a dielectric material. The method further includes forming an insulator material and metal material within the recess. The method further includes forming a contact in direct electrical contact with the metal material.Type: GrantFiled: October 25, 2016Date of Patent: August 1, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Veeraraghavan S. Basker, Kangguo Cheng, Ali Khakifirooz, Juntao Li
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Patent number: 9722068Abstract: Provided are semiconductor devices and methods of manufacturing the same. A semiconductor device may include a source, a drain, a semiconductor element between the source and the drain, and a graphene layer that is provided on the source and the semiconductor element and is spaced apart from the drain. Surfaces of the source and the drain are substantially co-planar with a surface of the semiconductor element. The semiconductor element may be spaced apart from the source and may contact the drain. The graphene layer may have a planar structure. A gate insulating layer and a gate may be provided on the graphene layer. The semiconductor device may be a transistor. The semiconductor device may have a barristor structure. The semiconductor device may be a planar type graphene barristor.Type: GrantFiled: September 16, 2014Date of Patent: August 1, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Xianyu Wenxu, Yongsung Kim, Changyoul Moon, Yongyoung Park, Wooyoung Yang, Jeongyub Lee, Jooho Lee
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Patent number: 9722095Abstract: A novel semiconductor device including an oxide semiconductor is provided. In particular, a planar semiconductor device including an oxide semiconductor is provided. A semiconductor device including an oxide semiconductor and having large on-state current is provided. The semiconductor device includes an oxide insulating film, an oxide semiconductor film over the oxide insulating film, a source electrode and a drain electrode in contact with the oxide semiconductor film, a gate insulating film between the source electrode and the drain electrode, and a gate electrode overlapping the oxide semiconductor film with the gate insulating film. The oxide semiconductor film includes a first region overlapped with the gate electrode and a second region not overlapped with the gate electrode, the source electrode, and the drain electrode. The first region and the second region have different impurity element concentrations.Type: GrantFiled: February 16, 2017Date of Patent: August 1, 2017Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Junichi Koezuka, Masami Jintyou, Yukinori Shima, Takashi Hamochi, Yasutaka Nakazawa, Shunpei Yamazaki
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Patent number: 9722118Abstract: A method for the production of a photovoltaic module comprising back-contact solar cells. A lower encapsulating layer, followed by an alignment and an application of the lower encapsulating layer to the inner surface of the back-contact back-sheet. The lower encapsulating layer, comprises a lower surface facing the back-contact back-sheet and an upper surface opposite the lower surface. The method includes adhesion of one or more predetermined portions of the lower surface of the encapsulating layer to the back-contact back-sheet, having each portion a predetermined superficial area which is lower than the total area of the lower surface of the lower encapsulating layer. The adhesion of the lower encapsulating layer is followed by the application of the lower encapsulating layer to the back-contact back-sheet.Type: GrantFiled: December 11, 2013Date of Patent: August 1, 2017Assignee: EBFOIL S.R.L.Inventors: Elisa Baccini, Luigi Marras, Bruno Bucci
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Patent number: 9716169Abstract: A lateral double diffused metal oxide semiconductor field-effect transistor includes semiconductor substrates, body regions positioned in the semiconductor substrates, drift regions positioned in the semiconductor substrates, source regions and a body leading-out region which are positioned in the body regions and spaced from the drift regions, a field region and drain regions which are positioned in the drift regions, and gates positioned on the surfaces of the semiconductor substrates to partially cover the body regions, the drift regions and the field region, wherein the field region is of a finger-like structure and comprises a plurality of strip field regions which extend from the source regions to the drain regions and are isolated by the active regions; and the strip field regions provided with strip gate extending regions extending from the gates.Type: GrantFiled: August 15, 2014Date of Patent: July 25, 2017Assignee: CSMC TECHNOLOGIES FABI CO., LTD.Inventors: Feng Huang, Guipeng Sun, Guangtao Han