Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate, wherein the substrate comprises a first region and a second region; forming a high-k dielectric layer on the first region and the second region; forming a first bottom barrier metal (BBM) layer on the high-k dielectric layer of the first region and the second region; forming a stop layer on the first region and the second region; removing the stop layer on the second region; and forming a second BBM layer on the first region and the second region.

Abstract: A method of manufacturing a light emitting device includes: providing an assembly comprising: a package comprising: a resin member having an inner side surface defining a recess, and a lead frame supported by the resin member and arranged at a bottom surface of the recess, and a light emitting element electrically connected to the lead frame; and forming a reflective film containing particles of a first light reflective substance on at least a portion of an outer surface of the resin member corresponding to the recess. The first light reflective substance comprises particles of a white pigment. A reflectance of the reflective film is higher than a reflectance of the resin member.

Abstract: A display panel includes a gate line, a data line, a first testing pad, a second testing pad, and a switching circuit. The gate line receives a gate-driving signal from a first node. The data line receives a data signal from a second node. The first testing pad transmits the gate-driving signal via one of a first reserved path and a first transmission path to the first node. The second testing pad transmits the data signal via one of a second reserved path and a second transmission path to the second node. The switching circuit selectively connects the first transmission path to the first node and connects the second transmission path to the second node. The first testing pad is connected to the first node via the first reserved path, and the second testing pad is connected to the second node via the second reserved path.

Abstract: Photosensitive logic inverter, in particular of the CMOS type, formed of a transistor of type P and of a transistor of type N of which the respective threshold voltages can be modulated according to the quantity of photons received by a photosensitive zone provided opposite these transistors.

Abstract: The reliability of a transistor including an oxide semiconductor can be improved by suppressing a change in electrical characteristics. A transistor included in a semiconductor device includes a first oxide semiconductor film over a first insulating film, a gate insulating film over the first oxide semiconductor film, a second oxide semiconductor film over the gate insulating film, and a second insulating film over the first oxide semiconductor film and the second oxide semiconductor film. The first oxide semiconductor film includes a channel region in contact with the gate insulating film, a source region in contact with the second insulating film, and a drain region in contact with the second insulating film. The second oxide semiconductor film has a higher carrier density than the first oxide semiconductor film.

Abstract: Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips supported by a scaffolding structure, the scaffolding structure defined by a first scaffolding trench and at least one additional scaffolding trench, the first scaffolding trench comprising a bottom surface having a width and a sidewall having a height extending from the bottom surface to define a lowermost trench in a scaffolding layer, the at least one additional scaffolding trench overlaying the first scaffolding trench having a sidewall having a height and a width, wherein the width of the at least one scaffolding trench is greater than the first scaffolding trench width to define a first stair between the first scaffolding trench and the at least one additional trench; a first chip secured to the first scaffolding trench having a height less than the first scaffolding trench sidewall height; and at least one additional chip secured to and supported by the

Abstract: According to one embodiment, a semiconductor memory device includes first conductive layers extending in a first direction and stacked in a second direction intersecting the first direction, a first semiconductor layer extending in the second direction and including a material having one of a first conductivity type and a second conductivity type, a first insulation layer disposed inside the first semiconductor layer, a second conductive layer disposed inside the first insulation layer, and a variable resistance layer disposed between the first conductive layers and the first semiconductor layer.

Abstract: A low-power wireless ionizing radiation measurement system is provided that is intended to be used in a wearable dosimeter for occupational radiation monitoring.

Abstract: An organic EL display device includes: a TFT substrate that includes a display area in which pixels are arranged in a matrix; and a color filter substrate that is provided to face the TFT substrate and includes an area transmitting light in a predetermined wavelength range for each of the pixels. Each of the pixels of the TFT substrate includes a pair of electrodes, at least two light emission layers that are arranged between the pair of electrodes, and a charge generation layer that is arranged between the at least two light emission layers, is a layer to generate a pair of positive and negative charges, and has different film thicknesses in accordance with the predetermined wavelength range of the corresponding area.

Abstract: A display device and a method for manufacturing the same are provided. The display device includes a first substrate, a second substrate and a light curable sealant. The first substrate has a displaying area and a non-displaying area, in which the displaying area includes a pixel array, and the non-displaying area includes a driving circuit. The driving circuit includes at least a capacitor which is made of transparent conductive material. The second substrate has an opaque area. The light curable sealant is located between the first substrate and the second substrate. When viewing from a normal vector of the first substrate or the second substrate, the light curable sealant, the capacitor and the opaque area are at least partially overlapped with each other.

Abstract: A semiconductor device including a non-volatile memory (NVM) cell and method of making the same are disclosed. The semiconductor device includes a metal-gate logic transistor formed on a logic region of a substrate, and the NVM cell integrally formed in a first recess in a memory region of the same substrate, wherein the first recess is recessed relative to a first surface of the substrate in the logic region. Generally, the metal-gate logic transistor further including a planarized surface above and substantially parallel to the first surface of the substrate in the logic region, and the NVM cell is arranged below an elevation of the planarized surface of the metal-gate. In some embodiments, logic transistor is a High-k Metal-gate (HKMG) logic transistor with a gate structure including a metal-gate and a high-k gate dielectric. Other embodiments are also disclosed.

Abstract: According to an embodiment, a semiconductor memory device comprises first wiring lines, second wiring lines, and first variable resistance elements. The first wiring lines are arranged in a first direction and have as their longitudinal direction a second direction intersecting the first direction. The second wiring lines are arranged in the second direction and have the first direction as their longitudinal direction. The first variable resistance elements are respectively provided at intersections of the first wiring lines and the second wiring lines. In addition, this semiconductor memory device comprises a first contact extending in a third direction that intersects the first direction and second direction and having one end thereof connected to the second wiring line. The other end and a surface intersecting the first direction of this first contact are covered by a first conductive layer.

Abstract: An embedded passive chip device includes a chip body and a functional layered structure. The chip body has a circuit-forming surface that is formed with a recess. The functional layered structure is formed on the chip body and includes a conductive layer that has at least a portion which covers at least partially the circuit-forming surface, and a magnetic layer that is disposed within the recess and that is inductively coupled to the conductive layer for generating inductance. A method of making the embedded passive chip device is also disclosed.

Abstract: A die interconnect system having a first die with a plurality of connection pads, and a ribbon lead extending from the first die, the ribbon lead having a plurality of metal cores with a core diameter, and a dielectric layer surrounding the metal core with a dielectric thickness, with at least a portion of dielectric being fused between adjacent metal cores along the length of the plurality of metal cores, and an outer metal layer attached to ground.

Abstract: A passive chip device includes a chip body, a conductive coil and a surface-mount contact unit. The chip body is in the form of a single piece, and has two opposite end faces and a first surface which is between the end faces. The conductive coil is deposited on and surrounding the chip body. The surface-mount contact unit includes two spaced apart conductive terminal contacts. Each of the terminal contacts extends from a respective one of the end faces to the first surface and connects to a respective one of end portions of the coil. The method of making the passive chip device is also disclosed.

Abstract: A magnetic junction usable in magnetic devices is described. The magnetic junction includes a reference layer, a free layer, a nonmagnetic spacer layer between the reference and free layers, and a rare earth-transition metal (RE-TM) layer in the reference and/or free layers. The free layer is switchable between stable magnetic states when a write current is passed through the magnetic junction. If the RE-TM layer is in the free layer then the RE-TM layer is between hard and soft magnetic layers in the free layer. In this aspect, the RE-TM layer has a standby magnetic moment greater than a write magnetic moment. If the RE-TM layer is in the reference layer, then the magnetic junction includes a second RE-TM layer. In this aspect, a first saturation magnetization quantity of the RE-TM layer matches a second saturation magnetization quantity of the second RE-TM layer over an operating temperature range.

Abstract: A method of fabricating a memory device includes forming an etching object layer and a lower sacrificial layer on a substrate, and forming an upper sacrificial pattern structure on the lower sacrificial layer. The upper sacrificial pattern structure includes a pad portion and a line portion on the lower sacrificial layer. An upper spacer is formed by covering a side wall of the upper sacrificial pattern structure. A lower sacrificial pattern structure including a lower sacrificial pad portion and a lower sacrificial line portion is formed by etching the lower sacrificial layer, by using the upper sacrificial pad portion and the upper spacer as a mask. A lower spacer layer is formed by covering the lower sacrificial pattern structure. A lower mask pattern including at least one line mask, bridge mask, and pad mask, is formed by etching the lower spacer layer and the lower sacrificial pattern structure.

Abstract: The present disclosure is directed toward carbon based diodes, carbon based resistive change memory elements, resistive change memory having resistive change memory elements and carbon based diodes, methods of making carbon based diodes, methods of making resistive change memory elements having carbon based diodes, and methods of making resistive change memory having resistive change memory elements having carbons based diodes. The carbon based diodes can be any suitable type of diode that can be formed using carbon allotropes, such as semiconducting single wall carbon nanotubes (s-SWCNT), semiconducting Buckminsterfullerenes (such as C60 Buckyballs), or semiconducting graphitic layers (layered graphene). The carbon based diodes can be pn junction diodes, Schottky diodes, other any other type of diode formed using a carbon allotrope. The carbon based diodes can be placed at any level of integration in a three dimensional (3D) electronic device such as integrated with components or wiring layers.

Abstract: A method of removing post-laser debris from a wafer includes, for an embodiment, forming a sacrificial layer over a layer to be patterned, patterning the sacrificial layer and the layer to be patterned using laser ablation, and removing the sacrificial layer and debris deposited on the sacrificial layer with water. The sacrificial layer includes a water soluble binder and a water soluble ultraviolet (UV) absorbent. Systems for removing the post-laser debris are also described.

Abstract: A change in electrical characteristics of a semiconductor device including an interlayer insulating film over a transistor including an oxide semiconductor as a semiconductor film is suppressed. The structure includes a first insulating film which includes a void portion in a step region formed by a source electrode and a drain electrode over the semiconductor film and contains silicon oxide as a component, and a second insulating film containing silicon nitride, which is provided in contact with the first insulating film to cover the void portion in the first insulating film. The structure can prevent the void portion generated in the first insulating film from expanding outward.