Abstract: A package structure includes at least one semiconductor die, a plurality of hollow cylinders, an insulating encapsulant, a redistribution layer and through holes. The plurality of hollow cylinders is surrounding the at least one semiconductor die. The insulating encapsulant has a top surface and a bottom surface opposite to the top surface, wherein the insulating encapsulant encapsulates the at least one semiconductor die and the plurality of hollow cylinders. The redistribution layer is disposed on the top surface of the insulant encapsulant and over the at least one semiconductor die. The through holes are penetrating through the plurality of hollow cylinders.

Abstract: A method of manufacturing a double magnetic tunnel junction device is provided. The method includes forming a first free layer, forming a first tunnel barrier layer on the free layer, forming a reference layer on the first tunnel barrier layer, forming a second tunnel barrier layer on the reference layer, and forming a second free layer on the second tunnel barrier layer. An area of the second free layer is less than an area of the first free layer. Also, the first free layer, the first tunnel barrier layer and the reference layer are a first magnetic tunnel junction, and the reference layer, the second tunnel barrier layer and the second free layer are a second magnetic tunnel junction.

Abstract: According to one embodiment, a magnetic memory device includes a substrate, a first layer stack, and a second layer stack at a same side of the first layer stack relative to the substrate, and farther than the first layer stack from the substrate. Each of the first and second layer stack includes a reference layer, a tunnel barrier layer provided in a direction relative to the reference layer, the direction being perpendicular to the substrate, a storage layer provided in the direction relative to the tunnel barrier layer, and a first nonmagnetic layer provided in the direction relative to the storage layer. A heat absorption rate of the first nonmagnetic layer of the first layer stack is lower than a heat absorption rate of the first nonmagnetic layer of the second layer stack.

Abstract: A package substrate for connecting together semiconductor devices with other semiconductor device packages. The package substrate includes an exposed core layer with at least one via exposing a conductive layer of the package substrate. A first portion of the package substrate may include a solder mask on top and bottom surfaces. A first semiconductor device may be connected to the first portion of the package substrate. Layers of a second portion of the package substrate are removed to expose a core layer and vias are created in the exposed core layer to expose the conductive layer. Conducive material at least partially filling the vias may be used to connect a semiconductor device package to the second portion of the package substrate. The semiconductor device packages may communicate through conductive layers in the package substrate. The package substrate may be used to connect the semiconductor packages to a motherboard.

Abstract: According to one embodiment, a magnetic device includes a layer stack. The layer stack includes a first ferromagnetic layer, a second ferromagnetic layer, a first nonmagnetic layer between the first ferromagnetic layer and the second ferromagnetic layer, and a second nonmagnetic layer. The first ferromagnetic layer is interposed between the second nonmagnetic layer and the first nonmagnetic layer. The first nonmagnetic layer and the second nonmagnetic layer contain a magnesium oxide (MgO). The first ferromagnetic layer contains a higher amount of boron (B) at an interface with the first nonmagnetic layer than at an interface with the second nonmagnetic layer.

Abstract: The invention comprises a novel composite multi-stack seed layer (CMSL) having lattice constant matched crystalline structure with the Co layer in above perpendicular magnetic pinning layer (pMPL) so that an excellent epitaxial growth of magnetic super lattice pinning layer [Co/(Pt, Pd or Ni)]n along its FCC (111) orientation can be achieved, resulting in a significant enhancement of perpendicular magnetic anisotropy (PMA) for perpendicular spin-transfer-torque magnetic-random-access memory (pSTT-MRAM) using perpendicular magnetoresistive elements as basic memory cells which potentially replace the conventional semiconductor memory used in electronic chips, especially mobile chips for power saving and non-volatility.

Abstract: Exemplary embodiments of the present disclosure provide a spin valve and a spintronic device comprising the same. The spin valve may comprise two or more magnetic layers stacked in sequence, wherein the spin valve further comprises at least one pair of nonmagnetic semiconductor layers arranged between any two adjacent magnetic layers among the two or more magnetic layers, wherein a built-in electric field is formed between the at least one pair of nonmagnetic semiconductor layers.

Abstract: A method of singulating a silicon carbide (SiC) semiconductor wafer can include defining a cut within the silicon carbide (SiC) semiconductor wafer by performing a partial dicing operation where the SiC semiconductor wafer is aligned along a plane and the cut has a depth less than a first thickness of the SiC semiconductor wafer. The cut is aligned along a vertical direction orthogonal to the plane such that a portion of the SiC semiconductor wafer has a second thickness that extends between a bottom of the cut and an outer surface of the SiC semiconductor wafer. The method can further include defining a cleave, by performing a cleaving operation, through the portion of the SiC semiconductor wafer having the second thickness. The cleave can be aligned with the cut and extending to the outer surface of the SiC semiconductor wafer.

Abstract: A top pinned magnetic tunnel junction (MTJ) stack containing a magnetic pinned layered structure including a second magnetic pinned layer having strong perpendicular magnetic anisotropy (PMA) is provided. In the present application, the magnetic pinned layered structure includes a crystal grain growth controlling layer located between a first magnetic pinned layer having a body centered cubic (BCC) texture and the second magnetic pinned layer. The presence of the crystal grain growth controlling layer facilitates formation of a second magnetic pinned layer having a face centered cubic (FCC) texture or a hexagonal closed packing (HCP) texture which, in turn, promotes strong PMA to the second magnetic pinned layer of the magnetic pinned layered structure.

Abstract: In a described example, an apparatus includes a transistor formed on a semiconductor substrate, the transistor including: a transistor gate and an extended drain between the transistor gate and a transistor drain contact; a transistor source contact coupled to a source contact probe pad; a first dielectric layer covering the semiconductor substrate and the transistor gate; a source field plate on the first dielectric layer and coupled to a source field plate probe pad spaced from and electrically isolated from the source contact probe pad; and the source field plate capacitively coupled through the first dielectric layer to a first portion of the extended drain.

Abstract: A magnetic tunnel junction (MTJ) device includes a cylindrically-shaped pillar structure and a first ferromagnetic layer disposed on at least a portion of the pillar structure. The first ferromagnetic layer exhibits a magnetization that is changeable in the presence of at least one of an applied bias and heat. The MTJ device further includes a dielectric barrier disposed on at least a portion of the first ferromagnetic layer and a second ferromagnetic layer disposed on at least a portion of the dielectric barrier. The second ferromagnetic layer exhibits a magnetization that is fixed. The MTJ device is configured such that the first and second ferromagnetic layers and the dielectric barrier concentrically surround the pillar structure.

Abstract: A method of manufacturing a magnetic tunnel junction device is provided. The method includes forming a conical insulator core, forming a conductor layer on the insulator core, forming a magnetic free layer on the conductor layer, forming a barrier layer on the magnetic free layer, and forming a magnetic fixed layer on the barrier layer.

Abstract: A self-selecting memory cell may be composed of a memory material that changes threshold voltages based on the polarity of the voltage applied across it. Such a memory cell may be formed at the intersection of a conductive pillar and electrode plane in a memory array. A dielectric material may be formed between the memory material of the memory cell and the corresponding electrode plane. The dielectric material may form a barrier that prevents harmful interactions between the memory material and the material that makes up the electrode plane. In some cases, the dielectric material may also be positioned between the memory material and the conductive pillar to form a second dielectric barrier. The second dielectric barrier may increase the symmetry of the memory array or prevent harmful interactions between the memory material and an electrode cylinder or between the memory material and the conductive pillar.

Abstract: A refractory metal-containing etch stop layer, a ruthenium etch stop layer, and a conductive material layer can be sequentially formed over an electrode layer and a selector material layer. A sequence of anisotropic etch processes can be employed to etch the conductive material layer selective to the ruthenium etch stop layer, to etch the ruthenium etch stop layer selective to the refractory metal-containing etch stop layer, and to etch the refractory metal-containing etch stop layer within minimal overetch into the electrode layer. The selector material layer can be subsequently anisotropically etched without exposure to the plasma of etchant gases for etching the refractory metal-containing etch stop layer and the conductive material layer, which may include a fluorine-containing plasma that can damage the selector material.

Abstract: A magnetoresistive device may include one or more electrodes or electrically conductive lines and a fixed region and a free region disposed between the electrodes or electrically conductive lines. The fixed region may have a fixed magnetic state and the free region may be configured to have a first magnetic state and a second magnetic state. The free region may store a first value when in the first magnetic state and store a second value when in the second magnetic state. The magnetoresistive device may further include a dielectric layer between the free region and the fixed region and a spin-Hall (SH) material proximate to at least a portion of the free region. An insertion layer may be disposed between the SH material and the free region.

Abstract: A spin-orbit-torque magnetization rotational element includes: a ferromagnetic metal layer, a magnetization direction of the ferromagnetic metal layer being configured to change; a spin-orbit torque wiring which extends in the first direction intersecting a lamination direction of the ferromagnetic metal layer and is joined to the ferromagnetic metal layer; and two via wires, each of which extends in a direction intersecting the spin-orbit torque wiring from a surface of the spin-orbit torque wiring opposite to a side with the ferromagnetic metal layer and is connected to a semiconductor circuit, wherein a via-to-via distance between the two via wires in the first direction is shorter than a width of the ferromagnetic metal layer in the first direction.

Abstract: The invention comprises a novel composite multi-stack seed layer (CMSL) having lattice constant matched crystalline structure with the Co layer in above perpendicular magnetic pinning layer (pMPL) so that an excellent epitaxial growth of magnetic super lattice pinning layer [Co/(Pt, Pd or Ni)]n along its FCC (111) orientation can be achieved, resulting in a significant enhancement of perpendicular magnetic anisotropy (PMA) for perpendicular spin-transfer-torque magnetic-random-access memory (pSTT-MRAM) using perpendicular magnetoresistive elements as basic memory cells which potentially replace the conventional semiconductor memory used in electronic chips, especially mobile chips for power saving and non-volatility.

Abstract: A magnetic junction usable in a magnetic device is described. The magnetic junction includes a free layer and an oxide interlayer on the free layer. The oxide interlayer includes at least one glass-forming agent. In some aspects, the magnetic junction includes a reference layer and a nonmagnetic spacer layer being between the reference layer and the free layer. The free layer is between the nonmagnetic spacer layer and the oxide interlayer.

Abstract: A magnetic tunnel junction (MTJ) stack structure having an enhanced write performance and thermal stability (i.e., retention) is provided which can be used as an element/component of a spin-transfer torque (STT) MRAM device. The improved write performance, particularly the write error rate slope as a function of write voltage (Vfrc) which is essential in defining the overdrive voltage needed to successfully write a bit at low write error floors, is provided by a MTJ stack structure in which a zirconium (Zr) cap layer is inserted between a MTJ capping layer and an etch stop layer.

Abstract: Exemplary embodiments of the present disclosure provide a spin valve and a spintronic device comprising the same. The spin valves may comprise two or more magnetic layers stacked in sequence, wherein any two adjacent magnetic layers among the two or more magnetic layers have different coercive forces, and at least one of the any two adjacent magnetic layers is a van der Waals magnetic layer, wherein the van der Waals magnetic layer refers to a magnetic layer made of a van der Waals magnetic material.