Abstract: A method of manufacturing and resultant device are directed to an inverted wide-base double magnetic tunnel junction device having both high-efficiency and high-retention arrays. The method includes a method of manufacturing, on a common stack, a high-efficiency array and a high-retention array for an inverted wide-base double magnetic tunnel junction device. The method comprises, for the high-efficiency array and the high-retention array, forming a first magnetic tunnel junction stack (MTJ2), forming a spin conducting layer on the MTJ2, and forming a second magnetic tunnel junction stack (MTJ1) on the spin conducting layer. The first magnetic tunnel junction stack for the high-retention array has a high-retention critical dimension (CD) (HRCD) that is larger than a high-efficiency CD (HECD) of the first magnetic tunnel junction stack for the high-efficiency array. The second magnetic tunnel junction stack (MTJ1) is shorted for the high-retention array and is not shorted for the high-efficiency array.

Abstract: The thickness of a display device including a touch sensor is reduced. Alternatively, the thickness of a display device having high display quality is reduced. Alternatively, a method for manufacturing a display device with high mass productivity is provided. Alternatively, a display device having high reliability is provided. Stacked substrates in each of which a sufficiently thin substrate and a relatively thick support substrate are stacked are used as substrates. One surface of the thin substrate of one of the stacked substrates is provided with a layer including a touch sensor, and one surface of the thin substrate of the other stacked substrate is provided with a layer including a display element. After the two stacked substrates are attached to each other so that the touch sensor and the display element face each other, the support substrate and the thin substrate of each stacked substrate are separated from each other.

Abstract: The material layer stack includes first and second magnetic tunnel junctions and a first top electrode formed on a top face of the stack. A shoulder is formed on a lateral face of the stack and divides the stack into a lower portion and an upper portion. A tunnel barrier of the first magnetic tunnel junction is comprised by the lower stack portion and a tunnel barrier of the second magnetic tunnel junction by the upper stack portion. A second top electrode is formed on the shoulder. Each magnetic tunnel junction is adapted to store a bit as a reconfigurable magnetoresistance of its magnetic electrodes. Preferably, a bottom face of the stack is connected to a conductor supporting current induced magnetic polarization switching for the first magnetic tunnel junction by spin-orbit torque. Magnetic polarization switching for the second magnetic tunnel junction is preferably achieved by spin-transfer torque.

Abstract: A magnetic memory device includes a substrate; a first magnetoresistive effect element; and a second magnetoresistive effect element provided at a side of the first magnetoresistive effect element opposite to a side of the first magnetoresistive effect element at which the substrate is provided. A heat absorption rate of the first magnetoresistive effect element is lower than a heat absorption rate of the second magnetoresistive effect element.

Abstract: A spin-orbit-torque magnetization rotational element includes: a ferromagnetic metal layer, a magnetization direction of the ferromagnetic metal layer being configured to change; a spin-orbit torque wiring which extends in the first direction intersecting a lamination direction of the ferromagnetic metal layer and is joined to the ferromagnetic metal layer; and two via wires, each of which extends in a direction intersecting the spin-orbit torque wiring from a surface of the spin-orbit torque wiring opposite to a side with the ferromagnetic metal layer and is connected to a semiconductor circuit, wherein a via-to-via distance between the two via wires in the first direction is shorter than a width of the ferromagnetic metal layer in the first direction.

Abstract: A semiconductor device includes a substrate, a first magnetic tunnel junction (MTJ) structure, a second MTJ structure, and an interconnection structure. The first MTJ structure, the second MTJ structure, and the interconnection structure are disposed on the substrate. The interconnection structure is located between the first MTJ structure and the second MTJ structure in a first horizontal direction, and the interconnection structure includes a first metal interconnection and a second metal interconnection. The second metal interconnection is disposed on and contacts the first metal interconnection.

Abstract: A method for fabricating semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, in which the MTJ stack includes a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer. Next, a top electrode is formed on the MTJ stack, the top electrode, the free layer, and the barrier layer are removed, a first cap layer is formed on the top electrode, the free layer, and the barrier layer, and the first cap layer and the pinned layer are removed to form a MTJ and a spacer adjacent to the MTJ.

Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).

Abstract: A semiconductor device includes a substrate, a first magnetic tunnel junction (MTJ) structure, a second MTJ structure, and an interconnection structure. The first MTJ structure, the second MTJ structure, and the interconnection structure are disposed on the substrate. The interconnection structure is located between the first MTJ structure and the second MTJ structure in a first horizontal direction, and the interconnection structure includes a first metal interconnection and a second metal interconnection. The second metal interconnection is disposed on and contacts the first metal interconnection. A material composition of the second metal interconnection is different from a material composition of the first metal interconnection.

Abstract: A device including a templating structure and a magnetic layer on the templating structure is described. The templating structure includes D and E. A ratio of D to E is represented by D1-xEx, with x being at least 0.4 and not more than 0.6. E includes a main constituent. The main constituent includes at least one of Al, Ga, and Ge. Further, E includes at least fifty atomic percent of the main constituent. D includes at least one constituent that includes Ir, D includes at least 50 atomic percent of the at least one constituent. The templating structure is nonmagnetic at room temperature. The magnetic layer includes at least one of a Heusler compound and an L10 compound, the magnetic layer being in contact with the templating structure.

Abstract: A resistive memory device includes a magnetic tunnel junction structure. The magnetic tunnel junction structure includes a free magnetic layer. The free magnetic layer includes a magnetic material configurable to host topological spin textures to tune a conductance state of the resistive memory device.

Abstract: A spin-orbit torque magnetoresistive random-access memory device formed by fabricating a spin-Hall-effect (SHE) layer above and in electrical contact with a transistor, forming a spin-orbit-torque (SOT) magnetoresistive random access memory (MRAM) cell stack disposed above and in electrical contact with the SHE rail, wherein the SOT-MRAM cell stack comprises a free layer, a tunnel junction layer, a reference layer, and a diode structure, forming a write line disposed in electrical contact with the SHE rail, forming a protective dielectric layer covering a portion of the SOT-MRAM cell stack, and forming a read line disposed above and adjacent to the diode structure.

Abstract: A method for manufacturing a memory device includes forming a via trench in a substrate and forming a via in the via trench. A lower portion of the via includes a first metal and an upper portion of the via includes a second metal that is different from the first metal. The method further includes forming a magnetic tunneling junction over the via and forming a top electrode over the magnetic tunneling junction.

Abstract: A magnetic memory device includes a magnetic tunnel junction (MTJ) stack, a spin-orbit torque (SOT) induction wiring disposed over the MTJ stack, a first terminal coupled to a first end of the SOT induction wiring, a second terminal coupled to a second end of the SOT induction wiring, and a selector layer coupled to the first terminal.

Abstract: A magnetization rotational element includes a spin-orbit torque wiring, and a first ferromagnetic layer which is located in a first direction with respect to the spin-orbit torque wiring and in which spins are injected from the spin-orbit torque wiring. The spin-orbit torque wiring has a plurality of spin generation layers and insertion layers located between the plurality of spin generation layers in the first direction. The insertion layers have a lower electrical resistivity than the spin generation layers.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a memory cell. In some embodiments, a memory film is deposited over a substrate and comprises a bottom electrode layer, a top electrode layer, and a data storage film between the top and bottom electrode layers. A hard mask film is deposited over the memory film and comprises a conductive hard mask layer. The top electrode layer and the hard mask film are patterned to respectively form a top electrode and a hard mask over the top electrode. A trimming process is performed to decrease a sidewall angle between a sidewall of the hard mask and a bottom surface of the hard mask. An etch is performed into the data storage film with the hard mask in place after the trimming process to form a data storage structure underlying the top electrode.

Abstract: A memory device, and a method of forming the same, includes a bottom electrode above an electrically conductive structure, the electrically conductive structure is embedded in an interconnect dielectric material. A magnetic tunnel junction stack located above the bottom electrode is formed by a magnetic reference layer above the bottom electrode, a tunnel barrier layer above the magnetic reference layer, and a laterally-recessed magnetic free layer above the tunnel barrier layer. Sidewall spacers surround the laterally-recessed magnetic free layer for confining an active region formed by the laterally-recessed magnetic free and the tunnel barrier layer.

Abstract: A memory device includes a substrate, a laminated structure and a memory string. The laminated structure is disposed on the substrate. The laminated structure includes a plurality of insulating layers and a plurality of conductive layers alternately stacked along a first direction. The memory string is accommodated in the laminated structure along the first direction. The memory string includes a memory layer and a channel layer, and the memory layer is disposed between the laminated structure and the channel layer. At least a portion of the memory layer and the insulating layers are overlapped along the first direction.

Abstract: A spin element according to the present embodiment includes a wiring, a laminate including a first ferromagnetic layer laminated on the wiring, a first conductive part and a second conductive part with the first ferromagnetic layer therebetween in a plan view in a lamination direction, and an intermediate layer which is in contact with the wiring and is between the first conductive part and the wiring, wherein a diffusion coefficient of a second element including the intermediate layer with respect to a first element including the wiring is smaller than a diffusion coefficient of a third element constituting the first conductive part with respect to the first element or a diffusion coefficient of the third element including the first conductive part with respect to the second element constituting the wiring is smaller than a diffusion coefficient of the third element with respect to the first element constituting the intermediate layer.

Abstract: A device including a templating structure and a magnetic layer is described. The templating structure includes D and E. A ratio of D to E is represented by D1-xEx, with x being at least 0.4 and not more than 0.6. E includes a main constituent. The main constituent includes at least one of Al, Ga, and Ge. E includes at least fifty atomic percent of the main constituent. D includes at least one constituent that includes Ir. D includes at least 50 atomic percent of the at least one constituent. The magnetic layer is on the templating structure and includes at least one of a Heusler compound and an L10 compound. The magnetic layer is in contact with the templating structure and being magnetic at room temperature.