Patents Examined by Jami Valentine Miller
  • Magnetic tunnel junction device
    Patent number: 11968908
    Abstract: In an embodiment, a method includes: forming a first inter-metal dielectric (IMD) layer over a semiconductor substrate; forming a bottom electrode layer over the first IMD layer; forming a magnetic tunnel junction (MTJ) film stack over the bottom electrode layer; forming a first top electrode layer over the MTJ film stack; forming a protective mask covering a first region of the first top electrode layer, a second region of the first top electrode layer being uncovered by the protective mask; forming a second top electrode layer over the protective mask and the first top electrode layer; and patterning the second top electrode layer, the first top electrode layer, the MTJ film stack, the bottom electrode layer, and the first IMD layer with an ion beam etching (IBE) process to form a MRAM cell, where the protective mask is etched during the IBE process.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: April 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tai-Yen Peng, Hui-Hsien Wei, Han-Ting Lin, Sin-Yi Yang, Yu-Shu Chen, An-Shen Chang, Qiang Fu, Chen-Jung Wang
  • Magnetic domain wall movement element and magnetic recording array
    Patent number: 11963461
    Abstract: A magnetic domain wall movement element according to the present embodiment includes a first ferromagnetic layer, a nonmagnetic layer, and a second ferromagnetic layer that are laminated in an order from a side close to a substrate. On a cross-section along a lamination direction and a second direction orthogonal to a first direction in which the first ferromagnetic layer extends in a plan view from the lamination direction, a shortest width of the first ferromagnetic layer in the second direction is shorter than a width of the nonmagnetic layer in the second direction.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: April 16, 2024
    Assignee: TDK CORPORATION
    Inventors: Takuya Ashida, Tatsuo Shibata
  • Spin-orbit torque (SOT) magnetoresistive random-access memory (MRAM) with low resistivity spin hall effect (SHE) write line
    Patent number: 11961544
    Abstract: Embodiments of the invention include a method for fabricating a magnetoresistive random-access memory (MRAM) structure and the resulting structure. A first type of metal is formed on an interlayer dielectric layer with a plurality of embedded contacts, where the first type of metal exhibits spin Hall effect (SHE) properties. At least one spin-orbit torque (SOT) MRAM cell is formed on the first type of metal. One or more recesses surrounding the at least one SOT-MRAM cell are created by recessing exposed portions of the first type of metal. A second type of metal is formed in the one or more recesses, where the second type of metal has lower resistivity than the first type of metal.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: April 16, 2024
    Assignee: International Business Machines Corporation
    Inventors: Julien Frougier, Dimitri Houssameddine, Ruilong Xie, Kangguo Cheng
  • Method for manufacturing memory device having resistance switching layer
    Patent number: 11963460
    Abstract: A method for manufacturing a memory device is provided. The method includes etching an opening in a first dielectric layer; forming a bottom electrode, a resistance switching element, and a top electrode in the opening in the first dielectric layer; forming a second dielectric layer over the bottom electrode, the resistance switching element, and the top electrode; and forming an electrode via connected to a top surface of the top electrode in the second dielectric layer.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: April 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Hsiang Tseng, Chih-Lin Wang, Yi-Huang Wu
  • Display apparatus having dam members
    Patent number: 11956989
    Abstract: A display apparatus includes: a substrate having a display area and a non-display area at least partially surrounding the display area; a plurality of pixels disposed in the display area of the substrate; a plurality of first projections disposed in the non-display area of the substrate extending along an edge of the substrate; and a second projection disposed on the substrate between the plurality of first projections and the display area, the second projection including a plurality of cavities arranged in a plurality of columns to limit flow of excess organic material during manufacture, wherein the cavities may be arranged in adjacent columns staggered from each other in a direction transverse to the columns.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: April 9, 2024
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sucheol Gong, Sungwoo Jung, Hun Kim, Kyungchan Chae
  • Magnetoresistive random access memory and method for fabricating the same
    Patent number: 11956973
    Abstract: A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first spin orbit torque (SOT) layer on the MTJ; forming a passivation layer around the MTJ; forming a second SOT layer on the first SOT layer and the passivation layer; and patterning the second SOT layer and the passivation layer.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: April 9, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hung-Chan Lin, Yu-Ping Wang
  • Regulator circuit package techniques
    Patent number: 11955437
    Abstract: Techniques are provided for containing magnetic fields generated by an integrated switching package and for reducing electromagnetic interference generated from an integrated switching package.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: April 9, 2024
    Assignee: Analog Devices International Unlimited Company
    Inventors: Leonard Shtargot, Zafer Kutlu, John Underhill Gardner
  • Semiconductor device comprising oxide semiconductor film comprising nanocrystal
    Patent number: 11935959
    Abstract: A change in electrical characteristics of a semiconductor device including an interlayer insulating film over a transistor including an oxide semiconductor as a semiconductor film is suppressed. The structure includes a first insulating film which includes a void portion in a step region formed by a source electrode and a drain electrode over the semiconductor film and contains silicon oxide as a component, and a second insulating film containing silicon nitride, which is provided in contact with the first insulating film to cover the void portion in the first insulating film. The structure can prevent the void portion generated in the first insulating film from expanding outward.
    Type: Grant
    Filed: October 12, 2022
    Date of Patent: March 19, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichi Koezuka, Toshinari Sasaki, Katsuaki Tochibayashi, Shunpei Yamazaki
  • MRAM structure for balanced loading
    Patent number: 11937515
    Abstract: Semiconductor device and methods of forming the same are provided. A semiconductor device according to one embodiment includes a dielectric layer including a top surface, a plurality of magneto-resistive memory cells disposed in the dielectric layer and including top electrodes, a first etch stop layer disposed over the dielectric layer, a common electrode extending through the first etch stop layer to be in direct contact with the top electrodes, and a second etch stop layer disposed on the first etch stop layer and the common electrode. Top surfaces of the top electrodes are coplanar with the top surface of the dielectric layer.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: March 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Fan Huang, Hsiang-Ku Shen, Liang-Wei Wang, Chen-Chiu Huang, Dian-Hau Chen, Yen-Ming Chen
  • Memory device with flat-top bottom electrodes and methods for forming the same
    Patent number: 11925032
    Abstract: A memory device includes an array of memory cells overlying a substrate and located in a memory array region. Each of the memory cells includes a bottom electrode, a vertical stack containing a memory element and a top electrode, and dielectric sidewall spacers located on sidewalls of each vertical stack. The bottom electrode comprises a flat-top portion that extends horizontally beyond an outer periphery of the dielectric sidewall spacers. The device also includes a discrete etch stop dielectric layer over each of the memory cells that includes a horizontally-extending portion that extends over the flat-top portion of the bottom electrode. The device also includes metallic cell contact structures that contact a respective subset of the top electrodes and a respective subset of vertically-protruding portions of the discrete etch stop dielectric layer.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventor: Chung-Chiang Min
  • Semiconductor package including sheilding cover that covers molded body
    Patent number: 11923319
    Abstract: A method of fabricating a semiconductor package includes mounting at least one semiconductor chip to a package substrate, forming a shielding wall around the at least one semiconductor chip, forming a molded body on the package substrate in a space surrounded by the shielding wall, and forming a shielding cover covering the molding unit and in contact with the shielding wall.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: March 5, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Young-Woo Park
  • Semiconductor device
    Patent number: 11923261
    Abstract: A semiconductor chip is provided on a semiconductor circuit base on one surface of an insulating substrate. A reinforcement and balance base is provided on the one surface of the insulating substrate spaced to the semiconductor circuit base. The insulating substrate 4, the semiconductor circuit base, the semiconductor chip, and the reinforcement and balance base are sealed into a resin-molded sealing body. The sealing body has resin non-adhering portions.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: March 5, 2024
    Assignee: Sansha Electric Manufacturing Co., Ltd.
    Inventor: Koutarou Maeda
  • Interlayer exchange coupled multiplier
    Patent number: 11917924
    Abstract: A multiplier device for binary magnetic applied fields uses Interlayer Exchange Coupling (IEC) structure where two layers of ferromagnetic material are separated from each other by non-magnetic layers of electrically conductive material of atomic thickness, sufficient to generate anti-magnetic response in a magnetized layer. A plurality of regions on a top surface are activated with a magnetic field in a first direction for a 1 value and in an opposite direction for a 0 value, the multiplication result presented as magnetic field direction on a plurality of output ferromagnetic regions.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: February 27, 2024
    Assignee: Ceremorphic, Inc.
    Inventors: Venkat Mattela, Sanghamitra Debroy, Santhosh Sivasubramani
  • Memory device with electrically parallel source lines
    Patent number: 11910723
    Abstract: A memory device includes a memory cell array having a plurality of memory cells arranged in rows and columns, each row of memory cells being associated with a word line, each column of memory cells being associated with a bit line and a source line. Each memory cell includes: a storage device coupled to the bit line, the storage device being selectable between a first resistance state and a second resistance state in response to a bit line signal at the bit line; and a selection device connected in series with the storage device and coupled to the source line, the selection device being configured to provide access to the storage device in response to a word line signal at the word line. The memory device further includes a word-line driver and a bit-line driver. A first number of the source lines are connected in parallel.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Ku-Feng Lin
  • Perpendicular MTJ element having a cube-textured reference layer and methods of making the same
    Patent number: 11910721
    Abstract: The invention comprises a method of forming a novel magnetic pinning structure having a (100) textured or cube-textured reference layer through a non-epitaxial texturing approach so that an excellent coherent tunneling effect is achieved in a pMTJ element due to its texture structure of CoFe BCC (100)/MgO rocksalt (100)/CoFe BCC (100). Correspondingly, a high MR ratio and a high pinning strength on the reference layer can be achieved for perpendicular spin-transfer-torque magnetic-random-access memory (pSTT-MRAM) using perpendicular magnetoresistive elements as basic memory cells which potentially replace the conventional semiconductor memory used in electronic chips, especially mobile chips for power saving and non-volatility.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: February 20, 2024
    Inventors: Yimin Guo, Rongfu Xiao, Jun Chen
  • SOT-MRAM cell in high density applications
    Patent number: 11903326
    Abstract: In some embodiments, the present disclosure relates to a memory device that includes a spin orbit torque (SOT) layer arranged over a substrate. A magnetic tunnel junction (MTJ) structure may be arranged over the SOT layer. The MTJ structure includes a free layer, a reference layer, and a diffusion barrier layer disposed between the free layer and the reference layer. A first conductive wire is arranged below the SOT layer and coupled to the SOT layer. A second conductive wire is arranged below the SOT layer and coupled to the SOT layer. A third conductive wire is arranged over the MTJ structure. The memory device further includes a first selector structure arranged between the first conductive wire and the SOT layer.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: February 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming Yuan Song, Shy-Jay Lin
  • Spin element and magnetic memory
    Patent number: 11903327
    Abstract: This spin element includes: a current-carrying part that extends in a first direction; and an element part that is laminated on one surface of the current-carrying part, wherein the current-carrying part includes a first wiring and a second wiring in order from a side of the element part, and wherein both of the first wiring and the second wiring are metals and temperature dependence of resistivity of the first wiring is larger than temperature dependence of resistivity of the second wiring in at least a temperature range of ?40° C. to 100° C.
    Type: Grant
    Filed: November 9, 2022
    Date of Patent: February 13, 2024
    Assignee: TDK CORPORATION
    Inventor: Tomoyuki Sasaki
  • Magnetoresistive random access memory and method for fabricating the same
    Patent number: 11895926
    Abstract: A method for fabricating a semiconductor device includes the steps of first forming a first inter-metal dielectric (IMD) layer on a substrate and a metal interconnection in the first IMD layer, forming a magnetic tunneling junction (MTJ) and a top electrode on the metal interconnection, forming a spacer adjacent to the MTJ and the top electrode, forming a second IMD layer around the spacer, forming a cap layer on the top electrode, the spacer, and the second IMD layer, and then patterning the cap layer to form a protective cap on the top electrode and the spacer.
    Type: Grant
    Filed: November 3, 2020
    Date of Patent: February 6, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Ju-Chun Fan, Ching-Hua Hsu, Yi-Yu Lin, Hung-Yueh Chen
  • Magnetic junction memory device and reading method thereof
    Patent number: 11889703
    Abstract: A magnetic junction memory device is provided. The magnetic junction memory device including a sensing circuit including a sensing node, the sensing node being connected to a first end of a transistor and configured to change a voltage of the sensing node in accordance with a resistance of a magnetic junction memory cell, a gating voltage generator circuit configured to generate a gating voltage of the transistor using a reference resistor and a reference voltage, and a read circuit configured to read data from the magnetic junction memory cell using the reference voltage and the voltage of the sensing node.
    Type: Grant
    Filed: October 27, 2022
    Date of Patent: January 30, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chan Kyung Kim, Eun Ji Lee, Ji Yean Kim, Tae Seong Kim, Jae Wook Joo
  • Multi-chip package and method of providing die-to-die interconnects in same
    Patent number: 11876053
    Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: January 16, 2024
    Assignee: Intel Corporation
    Inventors: Henning Braunisch, Chia-Pin Chiu, Aleksandar Aleksov, Hinmeng Au, Stefanie M. Lotz, Johanna M. Swan, Sujit Sharan