Abstract: A spin element according to the present embodiment includes a wiring, a laminate including a first ferromagnetic layer laminated on the wiring, a first conductive part and a second conductive part with the first ferromagnetic layer therebetween in a plan view in a lamination direction, and an intermediate layer which is in contact with the wiring and is between the first conductive part and the wiring, wherein a diffusion coefficient of a second element including the intermediate layer with respect to a first element including the wiring is smaller than a diffusion coefficient of a third element constituting the first conductive part with respect to the first element or a diffusion coefficient of the third element including the first conductive part with respect to the second element constituting the wiring is smaller than a diffusion coefficient of the third element with respect to the first element constituting the intermediate layer.

Abstract: A device including a templating structure and a magnetic layer is described. The templating structure includes D and E. A ratio of D to E is represented by D1-xEx, with x being at least 0.4 and not more than 0.6. E includes a main constituent. The main constituent includes at least one of Al, Ga, and Ge. E includes at least fifty atomic percent of the main constituent. D includes at least one constituent that includes Ir. D includes at least 50 atomic percent of the at least one constituent. The magnetic layer is on the templating structure and includes at least one of a Heusler compound and an L10 compound. The magnetic layer is in contact with the templating structure and being magnetic at room temperature.

Abstract: Utilizing the topological character of patterns in 3D structures is beneficial for information storage, magnetic memory and logic systems. One embodiment describes the use of topological knots, exemplified by a Möbius strip, in which a spin traversing along the band for a complete cycle will recover its original position, while having rotated away from its original orientation. The spins can respond to an external magnetic field, but cannot achieve a ferromagnetic state, in which all magnetic moments are pointing in the same direction, due to the topological knot. 3D assemblies of such nano-Möbius strips may form prototype secure magnetic information storage devices that are secure and with extremely low levels of energy dissipation.

Abstract: An electronic device including a semiconductor memory is provided. The semiconductor memory includes: a substrate having a substantially horizontal upper surface; first to Nth layers (where N is a natural number of two or more) disposed in horizontal layers on the substrate and spaced apart from each other above the substrate in a vertical direction, wherein each of the first to Nth layers includes a plurality of conductive lines; an insulating layer disposed to fill spaces between the conductive lines; a hole having sidewalls that extends in the vertical direction through the conductive lines of the first to Nth layers and the insulating layer therebetween; a variable resistance layer disposed on the sidewalls of the hole; and a conductive pillar disposed to fill the hole in which the variable resistance layer is formed.

Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a magnetic tunnel junction (MTJ) structure including a free layer, a pinned layer, and a tunnel barrier layer, the free layer having a variable magnetization direction, the pinned layer having a fixed magnetization direction, the tunnel barrier layer being interposed between the free layer and the pinned layer; and a thermal stability enhanced layer (TSEL) including a homogeneous material having an Fe—O bond.

Abstract: The present invention provides a semiconductor packaging method and semiconductor device based on a molding process. In the packaging method, first, at least a portion of a compensation part is kept on at least a portion of a bonding region formed between a first adjoining surface of a semiconductor element and a second adjoining surface of a packaging component, to form a semi-finished product of a semiconductor device; then, during hardening of the packaging component, the compensation part is caused to undergo different degrees of deformation at different positions to compensate for a difference between a magnitude of deformation of the packaging component and a magnitude of deformation of the semiconductor element, so as to package the semiconductor element to form the semiconductor device. By means of the method, undesirable phenomena such as cracking and deformation of the surface of the semiconductor element can be avoided.

Abstract: According to one embodiment, a magnetic memory device includes: a plurality of first films and a plurality of second films stacked alternately; a first insulating layer passing through the plurality of first and second films; a second insulating layer passing through the plurality of first and second films and in contact with a surface of the first insulating layer; a first magnet including a first pillar portion provided between the second insulating layer and the plurality of first and second films, and a first terrace portion coupled to one end of the first pillar portion; a first interconnect layer coupled to the other end of the first pillar portion of the first magnet; and a first magnetoresistance effect element coupled to the first terrace portion of the first magnet.

Abstract: Embodiments of the present disclosure generally include spin-orbit torque magnetoresistive random-access memory (SOT-MRAM) devices and methods of manufacture thereof. The SOT-MRAM devices described herein include an SOT layer laterally aligned with a magnetic tunnel junction (MTJ) stack and formed over a trench in an interconnect. Thus, the presence of the SOT layer outside the area of the MTJ stack is eliminated, and electric current passes from the interconnect to the SOT layer by SOT-interconnect overlap. The devices and methods described herein reduce the formation of shunting current and enable the MTJ to self-align with the SOT layer in a single etching process.

Abstract: Semiconductor device and methods of forming the same are provided. A semiconductor device according to one embodiment includes a dielectric layer including a top surface, a plurality of magneto-resistive memory cells disposed in the dielectric layer and including top electrodes, a first etch stop layer disposed over the dielectric layer, a common electrode extending through the first etch stop layer to be in direct contact with the top electrodes, and a second etch slop layer disposed on the first etch stop layer and the common electrode. Top surfaces of the top electrodes are coplanar with the top surface of the dielectric layer.

Abstract: In one embodiment, the magnetic memory device includes a free layer structure having a variable magnetization direction. The free layer structure includes a first free layer, the first free layer being a first Heusler alloy; a coupling layer on the first free layer, the coupling layer including a metal oxide layer; and a second free layer on the metal oxide layer, the second free layer being a second Heusler alloy, the second Heusler alloy being different from the first Heusler alloy.

Abstract: Some embodiments include a memory device having a buried wordline, a shield plate, and an access device. The access device includes first and second diffusion regions and a channel region. The diffusion regions and the channel region are arranged vertically so that the channel region is between the first and second diffusion regions. The wordline is adjacent to a first side surface of the channel region, and the shield plate is adjacent to a second side surface of the channel region; with the first and second side surfaces being in opposing relation to one another. Some embodiments include methods of forming integrated assemblies.

Abstract: In an embodiment, a device includes: a magnetoresistive random access memory cell including: a bottom electrode; a reference layer over the bottom electrode; a tunnel barrier layer over the reference layer, the tunnel barrier layer including a first composition of magnesium and oxygen; a free layer over the tunnel barrier layer, the free layer having a lesser coercivity than the reference layer; a cap layer over the free layer, the cap layer including a second composition of magnesium and oxygen, the second composition of magnesium and oxygen having a greater atomic concentration of oxygen and a lesser atomic concentration of magnesium than the first composition of magnesium and oxygen; and a top electrode over the cap layer.

Abstract: According to one embodiment, a non-volatile memory device includes electrodes, an interlayer insulating film, at least one semiconductor layer, conductive layers, first and second insulating films. The electrodes are arranged in a first direction. The interlayer insulating film is provided between the electrodes. The semiconductor layer extends in the first direction in the electrodes and the interlayer insulating film. The conductive layers are provided between each of the electrodes and the semiconductor layer, and separated from each other in the first direction. The first insulating film is provided between the conductive layers and the semiconductor layer. The second insulating film is provided between each of the electrodes and the conductive layers, and extends between each of the electrodes and the interlayer insulating film adjacent to the each of the electrodes. A width of the conductive layers in the first direction is narrower than that of the second insulating film.

Abstract: The present disclosure provides an antenna package structure and an antenna packaging method. The package structure includes an antenna circuit chip, a first packaging layer, a first rewiring layer, an antenna structure, a second metal connecting column, a third packaging layer, a second antenna metal layer, and a second metal bump. The antenna circuit chip, the antenna structure, and the second antenna metal layer are interconnected by using the rewiring layer and the metal connecting column.

Abstract: The reliability of a transistor including an oxide semiconductor can be improved by suppressing a change in electrical characteristics. A transistor included in a semiconductor device includes a first oxide semiconductor film over a first insulating film, a gate insulating film over the first oxide semiconductor film, a second oxide semiconductor film over the gate insulating film, and a second insulating film over the first oxide semiconductor film and the second oxide semiconductor film. The first oxide semiconductor film includes a channel region in contact with the gate insulating film, a source region in contact with the second insulating film, and a drain region in contact with the second insulating film. The second oxide semiconductor film has a higher carrier density than the first oxide semiconductor film.

Abstract: A method of fabricating a semiconductor device including providing a substrate; forming first and second lower conductive patterns, the and second lower conductive patterns being buried in an interlayer dielectric layer; forming a capping layer on the interlayer dielectric layer and a dummy layer on the capping layer; etching an exposed upper portion of the first lower conductive pattern to form a trench; forming a metal layer that covers the interlayer dielectric layer and the dummy layer such that the metal layer fills the trench; forming a magnetic tunnel junction layer on the metal layer; performing a patterning process to form a memory cell; and forming a first protective layer that covers a lateral surface of the memory cell, wherein, in the patterning process, the metal layer on the top surface of the interlayer dielectric layer is etched to form a first bottom electrode in the trench.

Abstract: An illustrative memory cell disclosed herein includes a bottom electrode, a top electrode positioned above the bottom electrode and an MTJ (Magnetic Tunnel Junction) structure positioned above the bottom electrode and below the top electrode. In this example, the MTJ structure includes a first ferromagnetic material layer positioned above the bottom electrode, a non-magnetic insulation layer positioned above the first ferromagnetic material layer and a second ferromagnetic material layer positioned on the non-magnetic insulation layer, wherein there is a curved, non-planar interface between the non-magnetic insulation layer and the ferromagnetic material layer.

Abstract: A method for manufacturing an electronic device includes forming a first source layer including a trench, forming a first sacrificial layer in the trench, forming a first structure over the first source layer, wherein the first structure includes first material layers and second material layers which are alternately stacked over the each other, forming first openings passing through the first structure and extending to the first sacrificial layer, forming first channel layers in the first openings, forming a slit passing through the first structure and extending to the first sacrificial layer, forming a second opening by removing the first sacrificial layer through the slit, and forming a second source layer in the second opening, wherein the second source layer is coupled to the first channel layers.

Abstract: A semiconductor device including pixels arranged in a matrix of n rows and m columns, in which the pixels in the m-th column are shielded from light, is provided.

Abstract: A magnetic element is disclosed wherein a composite seed layer such as TaN/Mg enhances perpendicular magnetic anisotropy (PMA) in an overlying magnetic layer that may be a reference layer, free layer, or dipole layer. The first seed layer is selected from one or more of Ta, Zr, Nb, TaN, ZrN, NbN, and Ru. The second seed layer is selected from one or more of Mg, Sr, Ti, Al, V, Hf, B, and Si. A growth promoting layer made of NiCr or an alloy thereof is inserted between the seed layer and magnetic layer. In some embodiments, a first composite seed layer/NiCr stack is formed below the reference layer, and a second composite seed layer/NiCr stack is formed between the free layer and a dipole layer. The magnetic element has thermal stability to at least 400° C.