Patents Examined by Jami Valentine Miller
  • Magnetic junction memory device and reading method thereof
    Patent number: 11515357
    Abstract: A magnetic junction memory device is provided. The magnetic junction memory device including a sensing circuit including a sensing node, the sensing node being connected to a first end of a transistor and configured to change a voltage of the sensing node in accordance with a resistance of a magnetic junction memory cell, a gating voltage generator circuit configured to generate a gating voltage of the transistor using a reference resistor and a reference voltage, and a read circuit configured to read data from the magnetic junction memory cell using the reference voltage and the voltage of the sensing node.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: November 29, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chan Kyung Kim, Eun Ji Lee, Ji Yean Kim, Tae Seong Kim, Jae Wook Joo
  • Tunnel magnetoresistance sensor devices and methods of forming the same
    Patent number: 11513175
    Abstract: A semiconductor device may be provided including a first series portion and a second series portion electrically connected in parallel with the first series portion. The first series portion may include a first MTJ stack and a first resistive element electrically connected in series. The second series portion may include a second MTJ stack and a second resistive element electrically connected in series. The first resistive element may include a third MTJ stack and the second resistive element may include a fourth MTJ stack. The first, second, third, and fourth MTJ stacks may include a same number of layers, which may include a fixed layer, a free layer, and a tunnelling barrier layer between the fixed layer and the free layer. Alternatively, the first resistive element may include a first transistor and the second resistive element may include a second transistor.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: November 29, 2022
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Ping Zheng, Eng Huat Toh, Kazutaka Yamane, Shyue Seng Tan, Kiok Boone Elgin Quek
  • Semiconductor device comprising a void region insulating film
    Patent number: 11515426
    Abstract: A change in electrical characteristics of a semiconductor device including an interlayer insulating film over a transistor including an oxide semiconductor as a semiconductor film is suppressed. The structure includes a first insulating film which includes a void portion in a step region formed by a source electrode and a drain electrode over the semiconductor film and contains silicon oxide as a component, and a second insulating film containing silicon nitride, which is provided in contact with the first insulating film to cover the void portion in the first insulating film. The structure can prevent the void portion generated in the first insulating film from expanding outward.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: November 29, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichi Koezuka, Toshinari Sasaki, Katsuaki Tochibayashi, Shunpei Yamazaki
  • Magnetic device and magnetic random access memory
    Patent number: 11502241
    Abstract: A magnetic memory device includes a magnetic tunnel junction (MTJ) stack, a spin-orbit torque (SOT) induction wiring disposed over the MTJ stack, a first terminal coupled to a first end of the SOT induction wiring, a second terminal coupled to a second end of the SOT induction wiring, and a selector layer coupled to the first terminal.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: November 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: MingYuan Song, Shy-Jay Lin, William J. Gallagher, Hiroki Noguchi
  • Magnetoresistive memory device
    Patent number: 11502125
    Abstract: A magnetoresistive memory device according to one embodiment includes: first and second layer stacks, each of which includes: a first ferromagnetic layer having a magnetization directed in a first direction; a non-magnetic first conductive layer above the first ferromagnetic layer, a second ferromagnetic layer provided above the first conductive layer and having a magnetization directed in a second direction different from the first direction, a first insulating layer on an upper surface of the second ferromagnetic layer, and a third ferromagnetic layer above the first insulating layer. The second ferromagnetic layer of the second layer stack is thicker than the second ferromagnetic layer of the first layer stack.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: November 15, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Masaru Toko, Tadaomi Daibou, Junichi Ito, Taichi Igarashi, Tadashi Kai
  • Embedded memory devices
    Patent number: 11502242
    Abstract: A semiconductor device includes a base structure of an embedded memory device including a bottom electrode contact (BEC) landing pad within a memory area of the embedded memory device and a first metallization level having at least a first conductive line within a logic area of the embedded memory device, a cap layer disposed on the base structure, a BEC disposed through the cap layer on the BEC landing pad, a memory pillar disposed on the BEC and the cap layer, encapsulation layers encapsulating the memory pillar to protect the memory stack, and a second metallization level including a second conductive line surrounding the top electrode, a via disposed on the first conductive line such that the second via is below the top electrode, and a third conductive line disposed on the via to enable the memory pillar to be fitted between the first and second metallization levels.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: November 15, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ashim Dutta, Chih-Chao Yang, Michael Rizzolo, Theodorus E. Standaert
  • Magnetoresistance effect element and magnetic recording array
    Patent number: 11495739
    Abstract: A magnetoresistance effect element according to an embodiment includes: a spin orbit torque wiring extending in a first direction; a laminated body laminated on the spin orbit torque wiring and having a first ferromagnetic layer, a second ferromagnetic layer, and a non-magnetic layer between the first ferromagnetic layer and the second ferromagnetic layer; a conductive layer in contact with a side of the laminated body opposite to the spin orbit torque wiring; and a heat dissipation layer separated from the laminated body in the first direction and connected to the spin orbit torque wiring and the conductive layer.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: November 8, 2022
    Assignee: TDK CORPORATION
    Inventor: Eiji Komura
  • Semiconductor device including blocking layer
    Patent number: 11495736
    Abstract: A semiconductor device includes a plurality of magnetic tunnel junction (MTJ) structures in an interlayer insulating layer on a substrate. A blocking layer is on the interlayer insulating layer and the plurality of MTJ structures. An upper insulating layer is on the blocking layer. An upper interconnection is on the upper insulating layer. An upper plug is connected to the upper interconnection and a corresponding one of the plurality of MTJ structures and extends into the upper insulating layer and the blocking layer. The blocking layer includes a material having a higher absorbance constant than the upper insulating layer.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: November 8, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyungil Hong, Younghyun Kim, Junghwan Park, Sechung Oh, Jungmin Lee
  • Integrating embedded memory on CMOS logic using thin film transistors
    Patent number: 11489009
    Abstract: A semiconductor structure that includes a metal layer in a first interlayer dielectric that is above a semiconductor device. The semiconductor structure includes an embedded memory device on the metal layer. The embedded memory device has a first metal contact surrounded by a second interlayer dielectric. Additionally, the semiconductor structure includes a thin film transistor on the first metal contact. The thin film transistor is surrounded by a third interlayer dielectric. The third interlayer dielectric is over a portion of the embedded memory device and a portion of the second interlayer dielectric. The semiconductor structure includes a first portion of a channel of the thin film transistor covered a gate structure, where the channel is a layer of indium tin oxide.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: November 1, 2022
    Assignee: International Business Machines Corporation
    Inventors: Heng Wu, Julien Frougier, Bruce B. Doris, Chen Zhang, Ruilong Xie
  • Method for fabricating a semiconductor device
    Patent number: 11482666
    Abstract: A semiconductor substrate is provided. The semiconductor substrate has thereon a first dielectric layer, at least one conductive pattern disposed in the first dielectric layer, and a second dielectric layer covering the first dielectric layer and the at least one conductive pattern. A via opening is formed in the second dielectric layer. The via opening exposes a portion of the at least one conductive pattern. A polish stop layer is conformally deposited on the second dielectric layer and within the via opening. A barrier layer is conformally deposited on the polish stop layer. A tungsten layer is conformally deposited on the barrier layer. The tungsten layer and the barrier layer are polished until the polish stop layer on the second dielectric layer is exposed, thereby forming a via plug in the via opening. A bottom electrode layer is conformally deposited on the second dielectric layer and the via plug.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: October 25, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hsin-Jung Liu, Chau-Chung Hou, Ang Chan, Kun-Ju Li, Wen-Chin Lin
  • Tunnel magnetoresistance effect device and magnetic device using same
    Patent number: 11476413
    Abstract: A tunnel magnetoresistance effect (TMR) device includes an exchange coupling film having a first ferromagnetic layer, which is at least a portion of a fixed magnetic layer, and an antiferromagnetic layer laminated on the first ferromagnetic layer. The ferromagnetic layer includes an X(Cr—Mn) layer containing one or two or more elements X selected from the group consisting of the platinum group elements and Ni, and also containing Mn and Cr. The X(Cr—Mn) layer has a first region relatively near the first ferromagnetic layer, and a second region relatively far away from the first ferromagnetic layer, and the content of Mn in the first region is higher than that in the second region.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: October 18, 2022
    Assignee: ALPS ALPINE CO., LTD.
    Inventors: Masamichi Saito, Fumihito Koike
  • Perpendicular exchange bias with antiferromagnet for spin orbit coupling based memory
    Patent number: 11476412
    Abstract: An apparatus is provided which comprises: a magnetic junction including: a first structure comprising a magnet with an unfixed perpendicular magnetic anisotropy (PMA) relative to an x-y plane of a device; a second structure comprising one of a dielectric or metal; a third structure comprising a magnet with fixed PMA, wherein the third structure has an anisotropy axis perpendicular to the plane of the device, and wherein the third structure is adjacent to the second structure such that the second structure is between the first and third structures; a fourth structure comprising an antiferromagnetic (AFM) material, the fourth structure adjacent to the third structure; a fifth structure comprising a magnet with PMA, the fifth structure adjacent to the fourth structure; and an interconnect adjacent to the first structure, the interconnect comprising spin orbit material.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: October 18, 2022
    Assignee: Intel Corporation
    Inventors: Tanay Gosavi, Sasikanth Manipatruni, Kaan Oguz, Noriyuki Sato, Kevin O'Brien, Benjamin Buford, Christopher Wiegand, Angeline Smith, Tofizur Rahman, Ian Young
  • SOT-MRAM cell in high density applications
    Patent number: 11469371
    Abstract: In some embodiments, the present disclosure relates to a memory device that includes a spin orbit torque (SOT) layer arranged over a substrate. A magnetic tunnel junction (MTJ) structure may be arranged over the SOT layer. The MTJ structure includes a free layer, a reference layer, and a diffusion barrier layer disposed between the free layer and the reference layer. A first conductive wire is arranged below the SOT layer and coupled to the SOT layer. A second conductive wire is arranged below the SOT layer and coupled to the SOT layer. A third conductive wire is arranged over the MTJ structure. The memory device further includes a first selector structure arranged between the first conductive wire and the SOT layer.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: October 11, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming Yuan Song, Shy-Jay Lin
  • Domain wall motion type magnetic recording element
    Patent number: 11469370
    Abstract: A magnetic domain wall movement type magnetic recording element includes: a first ferromagnetic layer which includes a ferromagnetic body; a non-magnetic layer which faces the first ferromagnetic layer; and a magnetic recording layer which faces a surface of the non-magnetic layer on a side opposite to the first ferromagnetic layer and extends in a first direction. The magnetic recording layer has a concave-convex structure on a second surface opposite to a first surface which faces the non-magnetic layer.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: October 11, 2022
    Assignee: TDK CORPORATION
    Inventors: Kuniyasu Ito, Tatsuo Shibata
  • MRAM stacks, MRAM devices and methods of forming the same
    Patent number: 11456100
    Abstract: Memory stacks, memory devices and method of forming the same are provided. A memory stack includes a spin-orbit torque layer, a magnetic bias layer and a free layer. The magnetic bias layer is in physical contact with the spin-orbit torque layer and has a first magnetic anisotropy. The free layer is disposed adjacent to the spin-orbit torque layer and has a second magnetic anisotropy perpendicular to the first magnetic anisotropy.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: September 27, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Shy-Jay Lin, Wilman Tsai, Ming-Yuan Song
  • Magnetoresistive random access memory and method for fabricating the same
    Patent number: 11456331
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a logic region and a magnetoresistive random access memory (MRAM) region, forming a magnetic tunneling junction (MTJ) on the MRAM region, forming a metal interconnection on the MTJ, forming a dielectric layer on the metal interconnection, patterning the dielectric layer to form openings, and forming the blocking layer on the patterned dielectric layer and the metal interconnection and into the openings.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: September 27, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Jia-Rong Wu, I-Fan Chang, Rai-Min Huang, Ya-Huei Tsai, Yu-Ping Wang
  • Composite seed structure to improve PMA for perpendicular magnetic pinning
    Patent number: 11450466
    Abstract: The invention comprises a novel composite seed structure (CSS) having lattice constant matched crystalline structure with the Co layer in above perpendicular magnetic pinning layer (pMPL) so that an excellent epitaxial growth of magnetic super lattice pinning layer [Co/(Pt, Pd or Ni)]n along its FCC (111) orientation can be achieved, resulting in a significant enhancement of perpendicular magnetic anisotropy (PMA) for perpendicular spin-transfer-torque magnetic-random-access memory (pSTT-MRAM) using perpendicular magnetoresistive elements as basic memory cells which potentially replace the conventional semiconductor memory used in electronic chips, especially mobile chips for power saving and non-volatility.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: September 20, 2022
    Inventors: Yimin Guo, Rongfu Xiao, Jun Chen
  • Magnetoresistive element having a giant interfacial perpendicular magnetic anisotropy and method of making the same
    Patent number: 11450467
    Abstract: A magnetoresistive element comprises a novel iPMA cap layer on a surface of a recording layer to induce a giant interfacial perpendicular magnetic anisotropy (G-iPMA) of the recording layer and a method of making the same. The recording layer comprises a first free layer immediately contacting to the tunnel barrier layer and having a body-centered cubic structure with a (100) texture, and a second free layer having a body-centered cubic structure with a (110) texture or a face-centered cubic structure with a (111) texture, and a crystal-breaking layer inserted between the first free layer and the second free layer.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: September 20, 2022
    Inventors: Yimin Guo, Rongfu Xiao, Jun Chen
  • Memory device with flat-top bottom electrodes and methods for forming the same
    Patent number: 11437431
    Abstract: A memory device includes an array of memory cells overlying a substrate and located in a memory array region. Each of the memory cells includes a bottom electrode, a vertical stack containing a memory element and a top electrode, and dielectric sidewall spacers located on sidewalls of each vertical stack. The bottom electrode comprises a flat-top portion that extends horizontally beyond an outer periphery of the dielectric sidewall spacers. The device also includes a discrete etch stop dielectric layer over each of the memory cells that includes a horizontally-extending portion that extends over the flat-top portion of the bottom electrode. The device also includes metallic cell contact structures that contact a respective subset of the top electrodes and a respective subset of vertically-protruding portions of the discrete etch stop dielectric layer.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: September 6, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventor: Chung-Chiang Min
  • Magnetic tunnel junction (MTJ) devices with a synthetic antiferromagnet (SAF) structure including a magnetic skyrmion
    Patent number: 11430943
    Abstract: A magnetic tunneling junction (MTJ) memory device including a free and fixed (reference) magnet between first and second electrodes, and a synthetic antiferromagnet structure (SAF) structure between the fixed magnet and one of the electrodes. The SAF structure includes a magnetic skyrmion. Two magnetic skyrmions within a SAF structure may have opposing polarity. A SAF structure may further include a coupling layer between two magnetic layers, as well as interface layers separated from the coupling layer by one of the magnetic layers. The coupling layer may have a spin-orbit coupling effect on the magnetic layers that is of a sign opposite that of the interface layers, for example to promote formation of the magnetic skyrmions.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: August 30, 2022
    Assignee: Intel Corporation
    Inventors: Kevin O'Brien, Kaan Oguz, Noriyuki Sato, Charles Kuo, Mark Doczy