Patents Examined by Jamie C Niesz
  • Patent number: 11127916
    Abstract: An optically functional layer (160) is formed over a part of a second surface (100b) of a substrate (100). A first electrode (110) is formed over the optically functional layer (160), and a second electrode (130) is formed over the first electrode (110). An organic layer (120) is located between the first electrode (110) and the second electrode (130) and includes a light emitting layer. A plurality of the second electrodes (130) are formed. At least a part of a region between the plurality of second electrodes (130) has optical transparency. At least a part of an edge of the second electrode (130) is located outside the optically functional layer (160).
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: September 21, 2021
    Assignee: PIONEER CORPORATION
    Inventors: Hiroaki Kitahara, Shigenori Murakami
  • Patent number: 11088314
    Abstract: The present disclosure provides an ultrasonic transducer and a method for manufacturing an ultrasonic transducer, a display substrate and a method for manufacturing a display substrate. The method for manufacturing the ultrasonic transducer includes: forming a via hole in a substrate; forming a structural layer on a side of the substrate, the structural layer cover the via hole; and etching the structural layer from a side of the substrate away from the structural layer by using the substrate formed with the via hole as a blocking layer, to form a cavity at a position of the structural layer corresponding to that of the via hole.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: August 10, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Lei Zhao
  • Patent number: 11088097
    Abstract: An electronic package apparatus is formed from a semiconductor substrate having a cavity formed therein. The cavity has a top surface, a bottom surface and a sidewall surface, and a spacer extending from the bottom surface to the top surface. The spacer is formed from a dielectric material and has at least one lateral dimension less than 0.1 cm.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: August 10, 2021
    Assignee: International Business Machines Corporation
    Inventor: Bucknell C. Webb
  • Patent number: 11063188
    Abstract: A light emitting device that is capable of achieving excellent color rendering property is provided. The light emitting device contains a light emitting element having a light emission peak wavelength within a range of 430 nm or more and 470 nm or less, and a fluorescent member. The fluorescent member contains a first fluorescent material that contains an Eu-activated alkaline earth aluminate, a second fluorescent material that contains a Mn-activated fluorogermanate, a third fluorescent material that contains a Ce-activated rare earth aluminate, and a fourth fluorescent material that contains an Eu-activated silicon nitride having Al and at least one of Sr and Ca.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: July 13, 2021
    Assignee: NICHIA CORPORATION
    Inventor: Kenji Asai
  • Patent number: 11063178
    Abstract: A semiconductor heterostructure for an optoelectronic device with improved light emission is disclosed. The heterostructure can include a first semiconductor layer having a first index of refraction n1. A second semiconductor layer can be located over the first semiconductor layer. The second semiconductor layer can include a laminate of semiconductor sublayers having an effective index of refraction n2. A third semiconductor layer having a third index of refraction n3 can be located over the second semiconductor layer. The first index of refraction n1 is greater than the second index of refraction n2, which is greater than the third index of refraction n3.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: July 13, 2021
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Alexander Dobrinsky
  • Patent number: 11011511
    Abstract: An ESD protection device includes a substrate having an active fin extending in a first direction, a plurality of gate structures extending in a second direction at a given angle with respect to the first direction and partially covering the active fin, an epitaxial layer in a recess on a portion of the active fin between the gate structures, an impurity region under the epitaxial layer, and a contact plug contacting the epitaxial layer. A central portion of the impurity region is thicker than an edge portion of the impurity region, in the first direction. The contact plug lies over the central portion of the impurity region.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: May 18, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-Lim Kang, Hyun-Jo Kim, Jong-Mil Youn, Soo-Hun Hong
  • Patent number: 11011593
    Abstract: This organic EL display apparatus is equipped with a substrate that has a surface with a drive circuit being formed on the surface and comprising a thin film transistor, a planarizing layer that makes the surface of the substrate planar by covering the drive circuit, and an organic light-emitting element that is formed upon the surface of the planarizing layer and is electrically connected to the drive circuit. The planarizing layer includes a first inorganic insulating layer being deposited upon the drive circuit, an organic insulating layer being deposited upon the first inorganic insulating layer, and a second inorganic insulating layer being deposited upon the organic insulating layer. The surface of the second inorganic insulating layer that faces the opposite direction from the organic insulating layer has an arithmetic mean roughness of no more than 50 nm.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: May 18, 2021
    Assignee: SAKAI DISPLAY PRODUCTS CORPORATION
    Inventor: Katsuhiko Kishimoto
  • Patent number: 10985332
    Abstract: A display device includes a plurality of islands and a bridge connecting the plurality of islands to each other. Each of the plurality of islands includes a flexible substrate, a thin film transistor positioned on a first surface of the flexible substrate, a first electrode connected to the thin film transistor, and a protective mask positioned on a second surface of the flexible substrate.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: April 20, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jae Min Shin, Seung Bae Kang, Jong Ho Hong, Gun Mo Kim, Min Woo Kim, Won Sang Park, Hye Jin Joo
  • Patent number: 10985173
    Abstract: According to an embodiment, a non-volatile storage device includes a first layer, a second layer formed on the first layer, a stacked body including a plurality of conductive films stacked on the second layer, and a semiconductor pillar which penetrates the stacked body and the second layer and reaches the first layer. The semiconductor pillar includes a semiconductor film formed along an extending direction of the semiconductor pillar, and a memory film which covers a periphery of the semiconductor film. The memory film includes a first portion formed between the stacked body and the semiconductor film and a second portion formed between the second layer and the semiconductor film. An outer periphery of the second portion in a plane perpendicular to the extending direction is wider than an outer periphery of the first portion on a second layer side of the stacked body.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: April 20, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masaaki Higuchi, Masaru Kito, Masao Shingu
  • Patent number: 10957544
    Abstract: A method for preserving interlevel dielectric in a gate cut region includes recessing a dielectric fill to expose cap layers of gate structures formed in a device region and in a cut region and forming a liner in the recess on top of the recessed dielectric fill. The liner includes a material to provide etch selectivity to protect the dielectric fill. The gate structures in the cut region are recessed to form a gate recess using the liner to protect the dielectric fill from etching. A gate material is removed from within the gate structure using the liner to protect the dielectric fill from etching. A dielectric gap fill is formed to replace the gate material and to fill the gate recess in the cut region.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: March 23, 2021
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Andrew M. Greene, Ryan O. Jung, Ruilong Xie
  • Patent number: 10943967
    Abstract: A display device includes a substrate including a pixel region and a peripheral region. A plurality of pixels is disposed in the pixel region of the substrate. Each of the plurality of pixels includes a light emitting element. Data lines and scan lines are connected to each of the plurality of pixels. A power line is configured to supply power to the plurality of pixels. The power line includes a plurality of first conductive lines and a plurality of second conductive lines intersecting the plurality of first conductive lines. The plurality of second conductive lines is arranged in a region between adjacent light emitting elements of the plurality of pixels. At least some of the plurality of second conductive lines extend in a direction oblique to a direction of extension of the data lines or the scan lines.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: March 9, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Yang Wan Kim, Byung Sun Kim, Jae Yong Lee, Chung Yi, Hyung Jun Park, Su Jin Lee
  • Patent number: 10937992
    Abstract: A light emitting device, a manufacturing method thereof and a display device are disclosed. The light emitting device includes a light-emitting unit, a structured light guide layer, a light guide unit and a patterned reflective layer. The light-emitting unit has a circuit substrate and multiple light emitting elements, and the light emitting elements are separately disposed on a surface of the circuit substrate. The structured light guide layer is disposed opposite the light-emitting unit, and has multiple accommodating slots and multiple light guide structures disposed between the two accommodating slots. Each accommodating slot is disposed in correspondence with each light emitting element, and the light guide structures are disposed on the bottom surface of the structured light guide layer. The light guide unit is disposed on the top surface of the structured light guide layer.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: March 2, 2021
    Assignee: GIO OPTOELECTRONICS CORP.
    Inventor: Chin-Tang Li
  • Patent number: 10892385
    Abstract: Silicone-containing adhesive layer formed by cyclic ring-opening polymerization and comprising amounts of an organic base and bonding a wavelength converting layer to a thickness of sapphire in a light-emitting diode (LED) apparatus. Methods enabling its uninhibited curing so as to achieve contaminant-free and debris-free adhesion between surfaces. LED apparatus designed and manufactured such that surfaces to be bonded together are prepared in a manner that facilitates use of high-refractive-index adhesives. A multi-step process involving two different concentrations of a catalyst is performed so as to fabricate highly-reliable, non-browning, and non-cracking high-refractive-index adhesives for light-emitting diode component fabrication.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: January 12, 2021
    Assignee: LUMILEDS LLC
    Inventors: April Dawn Schricker, Daniel Roitman, Nicolaas Joseph Martin Van Leth
  • Patent number: 10879428
    Abstract: Solid state transducer (“SST”) devices with selective wavelength reflectors and associated systems and methods are disclosed herein. In several embodiments, for example, an SST device can include a first emitter configured to emit emissions having a first wavelength and a second emitter configured to emit emissions having a second wavelength different from the first wavelength. The first and second emitters can be SST structures and/or converter materials. The SST device can further include a selective wavelength reflector between the first and second emitters. The selective wavelength reflector can be configured to at least substantially transmit emissions having the first wavelength and at least substantially reflect emissions having the second wavelength.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: December 29, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Martin F. Schubert, Vladimir Odnoblyudov
  • Patent number: 10854752
    Abstract: Techniques are disclosed for incorporating high mobility strained channels into fin-based NMOS transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, a germanium or silicon germanium film is cladded onto silicon fins in order to provide a desired tensile strain in the core of the fin, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and cladding deposition can occur at a plurality of locations within typical process flow. In various embodiments, fins may be formed with a minimum width (or later thinned) so as to improve transistor performance. In some embodiments, a thinned fin also increases tensile strain across the core of a cladded fin. In some cases, strain in the core may be further enhanced by adding an embedded silicon epitaxial source and drain.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: December 1, 2020
    Assignee: Intel Corporation
    Inventors: Stephen M. Cea, Roza Kotlyar, Harold W. Kennel, Glenn A. Glass, Anand S. Murthy, Willy Rachmady, Tahir Ghani
  • Patent number: 10847456
    Abstract: Techniques and circuitry are disclosed for efficiently implementing programmable memory array circuit architectures, including both non-volatile and volatile memories. The memory circuitry employs an antifuse scheme that includes an array of 1T bitcells, wherein each bitcell effectively contains one gate or transistor-like device that provides both an antifuse element and a selector device for that bitcell. In particular, the bitcell device has asymmetric trench-based source/drain contacts such that one contact forms a capacitor in conjunction with the spacer and gate metal, and the other contact forms a diode in conjunction with a doped diffusion area and the gate metal. The capacitor serves as the antifuse element of the bitcell, and can be programmed by breaking down the spacer. The diode effectively provides a Schottky junction that serves as a selector device which can eliminate program and read disturbs from bitcells sharing the same bitline/wordline.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: November 24, 2020
    Assignee: Intel Corporation
    Inventors: Ting Chang, Chia-Hong Jan, Walid M. Hafez
  • Patent number: 10825812
    Abstract: A semiconductor integrated circuit includes: a first well region of a first conductivity type; a second well region of a second conductivity type provided in an upper portion of the first well region; a first current suppression layer of a second conductivity type being provided to be separated from the first well region in a lower portion of a base-body of the second conductivity type directly under the first well region and having an impurity concentration higher than that of the base-body; and a second current suppression layer of the first conductivity type provided under the first current suppression layer so as to be exposed from a bottom surface of the base-body.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: November 3, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hiroshi Kanno, Masaharu Yamaji, Hitoshi Sumida
  • Patent number: 10811401
    Abstract: Embodiments described herein relate to maintaining alignment between materials having different coefficients of thermal expansion during a bonding process of a light emitting diode (LED) device. The LED device includes a LED array and a backplane. The LED array and the blackplane each include a plurality of electrodes. During a bonding process where the electrodes of the LED array and electrodes of a backplane are bonded together, an alignment material having a coefficient of thermal expansion different than a coefficient of thermal expansion of the material of the LED array is deposited between LEDs of the LED array.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: October 20, 2020
    Assignee: Facebook Technologies, LLC
    Inventor: William Padraic Henry
  • Patent number: 10804451
    Abstract: To provide a semiconductor light-emitting device with a multilayer film hardly peeled therefrom and a production method therefor. The light-emitting device has an uneven substrate having an uneven shape on a first surface, a first conduction type first semiconductor layer on the uneven shape of the uneven substrate, a light-emitting layer on the first semiconductor layer, a second conduction type second semiconductor layer on the light-emitting layer, and a third DBR covering at least a part of the first semiconductor layer, the light-emitting layer, and the second semiconductor layer. The light-emitting device is of a flip-chip type. In the periphery of the uneven substrate, the uneven shape has an exposed portion exposed without being covered by the first semiconductor layer. The third DBR covers at least a part of the exposed portion of the uneven shape.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: October 13, 2020
    Assignee: TOYODA GOSEI CO., LTD.
    Inventor: Kosuke Yahata
  • Patent number: 10777649
    Abstract: A quantum nano-tip (QNT) thin film, such as a silicon nano-tip (SiNT) thin film, for flash memory cells is provided to increase erase speed. The QNT thin film includes a first dielectric layer and a second dielectric layer arranged over the first dielectric layer. Further, the QNT thin film includes QNTs arranged over the first dielectric layer and extending into the second dielectric layer. A ratio of height to width of the QNTs is greater than 50 percent. A QNT based flash memory cell and a method for manufacture a SiNT based flash memory cell are also provided.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: September 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsu-Hui Su, Chih-Ming Chen, Chia-Shiung Tsai, Chung-Yi Yu, Szu-Yu Wang